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| author | Evan Cheng <evan.cheng@apple.com> | 2009-07-17 22:13:25 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2009-07-17 22:13:25 +0000 |
| commit | 18fe458103cefed54c9e541dcc056cf69748e39f (patch) | |
| tree | 3e072273852d0481296347f10278907bacbc89b0 /llvm/test/CodeGen/X86/inline-asm-q-regs.ll | |
| parent | 72060b9719fe6832c2e592e096abf65cf2ade548 (diff) | |
| download | bcm5719-llvm-18fe458103cefed54c9e541dcc056cf69748e39f.tar.gz bcm5719-llvm-18fe458103cefed54c9e541dcc056cf69748e39f.zip | |
Fix x86 inline ams 'q' constraint support. In 32-bit mode, it's just like 'Q', i.e. EAX, EDX, ECX, EBX. In 64-bit mode, it just means all the i64r registers. Yeah, that makes sense.
llvm-svn: 76248
Diffstat (limited to 'llvm/test/CodeGen/X86/inline-asm-q-regs.ll')
| -rw-r--r-- | llvm/test/CodeGen/X86/inline-asm-q-regs.ll | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/inline-asm-q-regs.ll b/llvm/test/CodeGen/X86/inline-asm-q-regs.ll new file mode 100644 index 00000000000..19df81b231e --- /dev/null +++ b/llvm/test/CodeGen/X86/inline-asm-q-regs.ll @@ -0,0 +1,10 @@ +; RUN: llvm-as < %s | llc -march=x86-64 +; rdar://7066579 + + type { i64, i64, i64, i64, i64 } ; type %0 + +define void @t() nounwind { +entry: + %asmtmp = call %0 asm sideeffect "mov %cr0, $0 \0Amov %cr2, $1 \0Amov %cr3, $2 \0Amov %cr4, $3 \0Amov %cr8, $0 \0A", "=q,=q,=q,=q,=q,~{dirflag},~{fpsr},~{flags}"() nounwind ; <%0> [#uses=0] + ret void +} |
