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authorEvan Cheng <evan.cheng@apple.com>2008-09-24 00:05:32 +0000
committerEvan Cheng <evan.cheng@apple.com>2008-09-24 00:05:32 +0000
commite0add20c1b9e05b4d9ffdfa333d9a4448ff198f0 (patch)
treec26f5c08c642bc368ae3aed6843c06241ed6ef63 /llvm/test/CodeGen/X86/inline-asm-pic.ll
parente87abd26baadf18af9aae27532d5d6a859ed5357 (diff)
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Properly handle 'm' inline asm constraints. If a GV is being selected for the addressing mode, it requires the same logic for PIC relative addressing, etc.
llvm-svn: 56526
Diffstat (limited to 'llvm/test/CodeGen/X86/inline-asm-pic.ll')
-rw-r--r--llvm/test/CodeGen/X86/inline-asm-pic.ll10
1 files changed, 10 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/inline-asm-pic.ll b/llvm/test/CodeGen/X86/inline-asm-pic.ll
new file mode 100644
index 00000000000..04ad48d2921
--- /dev/null
+++ b/llvm/test/CodeGen/X86/inline-asm-pic.ll
@@ -0,0 +1,10 @@
+; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -relocation-model=pic | grep lea
+; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin -relocation-model=pic | grep call
+
+@main_q = internal global i8* null ; <i8**> [#uses=1]
+
+define void @func2() nounwind {
+entry:
+ tail call void asm "mov $1,%gs:$0", "=*m,ri,~{dirflag},~{fpsr},~{flags}"(i8** inttoptr (i32 152 to i8**), i8* bitcast (i8** @main_q to i8*)) nounwind
+ ret void
+}
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