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| author | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2017-11-30 12:12:19 +0000 |
|---|---|---|
| committer | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2017-11-30 12:12:19 +0000 |
| commit | 93ef145862e140ed880fd2eca404dc2641a12093 (patch) | |
| tree | 6e29f9874fc995008ef8e53a6375b06de67d33e6 /llvm/test/CodeGen/X86/handle-move.ll | |
| parent | bfb8fa5a160a943d9cf8d7254cf4375f2c135f2d (diff) | |
| download | bcm5719-llvm-93ef145862e140ed880fd2eca404dc2641a12093.tar.gz bcm5719-llvm-93ef145862e140ed880fd2eca404dc2641a12093.zip | |
[CodeGen] Print "%vreg0" as "%0" in both MIR and debug output
As part of the unification of the debug format and the MIR format, avoid
printing "vreg" for virtual registers (which is one of the current MIR
possibilities).
Basically:
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/%vreg([0-9]+)/%\1/g"
* grep -nr '%vreg' . and fix if needed
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/ vreg([0-9]+)/ %\1/g"
* grep -nr 'vreg[0-9]\+' . and fix if needed
Differential Revision: https://reviews.llvm.org/D40420
llvm-svn: 319427
Diffstat (limited to 'llvm/test/CodeGen/X86/handle-move.ll')
| -rw-r--r-- | llvm/test/CodeGen/X86/handle-move.ll | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/llvm/test/CodeGen/X86/handle-move.ll b/llvm/test/CodeGen/X86/handle-move.ll index 8acfd7ff209..a152f6db54e 100644 --- a/llvm/test/CodeGen/X86/handle-move.ll +++ b/llvm/test/CodeGen/X86/handle-move.ll @@ -8,8 +8,8 @@ ; %edx has a live range into the function and is used by the DIV32r. ; ; Here sinking a kill + dead def: -; 144B -> 180B: DIV32r %vreg4, %eax<imp-def>, %edx<imp-def,dead>, %EFLAGS<imp-def,dead>, %eax<imp-use,kill>, %edx<imp-use> -; %vreg4: [48r,144r:0) 0@48r +; 144B -> 180B: DIV32r %4, %eax<imp-def>, %edx<imp-def,dead>, %EFLAGS<imp-def,dead>, %eax<imp-use,kill>, %edx<imp-use> +; %4: [48r,144r:0) 0@48r ; --> [48r,180r:0) 0@48r ; DH: [0B,16r:0)[128r,144r:2)[144r,144d:1) 0@0B-phi 1@144r 2@128r ; --> [0B,16r:0)[128r,180r:2)[180r,180d:1) 0@0B-phi 1@180r 2@128r @@ -25,8 +25,8 @@ entry: } ; Same as above, but moving a kill + live def: -; 144B -> 180B: DIV32r %vreg4, %eax<imp-def,dead>, %edx<imp-def>, %EFLAGS<imp-def,dead>, %eax<imp-use,kill>, %edx<imp-use> -; %vreg4: [48r,144r:0) 0@48r +; 144B -> 180B: DIV32r %4, %eax<imp-def,dead>, %edx<imp-def>, %EFLAGS<imp-def,dead>, %eax<imp-use,kill>, %edx<imp-use> +; %4: [48r,144r:0) 0@48r ; --> [48r,180r:0) 0@48r ; DH: [0B,16r:0)[128r,144r:2)[144r,184r:1) 0@0B-phi 1@144r 2@128r ; --> [0B,16r:0)[128r,180r:2)[180r,184r:1) 0@0B-phi 1@180r 2@128r @@ -41,13 +41,13 @@ entry: ret i32 %add } -; Moving a use below the existing kill (%vreg5): -; Moving a tied virtual register def (%vreg11): +; Moving a use below the existing kill (%5): +; Moving a tied virtual register def (%11): ; -; 96B -> 120B: %vreg11<def,tied1> = SUB32rr %vreg11<tied0>, %vreg5 -; %vreg11: [80r,96r:1)[96r,144r:0) 0@96r 1@80r +; 96B -> 120B: %11<def,tied1> = SUB32rr %11<tied0>, %5 +; %11: [80r,96r:1)[96r,144r:0) 0@96r 1@80r ; --> [80r,120r:1)[120r,144r:0) 0@120r 1@80r -; %vreg5: [16r,112r:0) 0@16r +; %5: [16r,112r:0) 0@16r ; --> [16r,120r:0) 0@16r ; define i32 @f3(i32 %a, i32 %b) nounwind uwtable readnone ssp { |
