[X86] Enable fp128 as a legal type with SSE1 rather than with MMX.

FP128 values are passed in xmm registers so should be asssociated
with an SSE feature rather than MMX which uses a different set
of registers.

llc enables sse1 and sse2 by default with x86_64. But does not
enable mmx. Clang enables all 3 features by default.

I've tried to add command lines to test with -sse
where possible, but any test that returns a value in an xmm
register fails with a fatal error with -sse since we have no
defined ABI for that scenario.

llvm-svn: 370682

1 files changed, 30 insertions, 30 deletions

diff --git a/llvm/test/CodeGen/X86/fp128-select.ll b/llvm/test/CodeGen/X86/fp128-select.ll
index 503c7a9291e..134f1f38a6e 100644
--- a/llvm/test/CodeGen/X86/fp128-select.ll
+++ b/llvm/test/CodeGen/X86/fp128-select.ll
@@ -1,37 +1,37 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -O2 -mtriple=x86_64-linux-android -mattr=+mmx \
-; RUN:     -enable-legalize-types-checking | FileCheck %s --check-prefix=MMX
-; RUN: llc < %s -O2 -mtriple=x86_64-linux-gnu -mattr=+mmx \
-; RUN:     -enable-legalize-types-checking | FileCheck %s --check-prefix=MMX
-; RUN: llc < %s -O2 -mtriple=x86_64-linux-android \
-; RUN:     -enable-legalize-types-checking | FileCheck %s
-; RUN: llc < %s -O2 -mtriple=x86_64-linux-gnu \
-; RUN:     -enable-legalize-types-checking | FileCheck %s
+; RUN: llc < %s -O2 -mtriple=x86_64-linux-android -mattr=+sse \
+; RUN:     -enable-legalize-types-checking | FileCheck %s --check-prefix=SSE
+; RUN: llc < %s -O2 -mtriple=x86_64-linux-gnu -mattr=+sse \
+; RUN:     -enable-legalize-types-checking | FileCheck %s --check-prefix=SSE
+; RUN: llc < %s -O2 -mtriple=x86_64-linux-android -mattr=-sse \
+; RUN:     -enable-legalize-types-checking | FileCheck %s --check-prefix=NOSSE
+; RUN: llc < %s -O2 -mtriple=x86_64-linux-gnu -mattr=-sse \
+; RUN:     -enable-legalize-types-checking | FileCheck %s --check-prefix=NOSSE
 
 define void @test_select(fp128* %p, fp128* %q, i1 zeroext %c) {
-; MMX-LABEL: test_select:
-; MMX:       # %bb.0:
-; MMX-NEXT:    testl %edx, %edx
-; MMX-NEXT:    jne .LBB0_1
-; MMX-NEXT:  # %bb.2:
-; MMX-NEXT:    movaps {{.*}}(%rip), %xmm0
-; MMX-NEXT:    movaps %xmm0, (%rsi)
-; MMX-NEXT:    retq
-; MMX-NEXT:  .LBB0_1:
-; MMX-NEXT:    movups (%rdi), %xmm0
-; MMX-NEXT:    movaps %xmm0, (%rsi)
-; MMX-NEXT:    retq
+; SSE-LABEL: test_select:
+; SSE:       # %bb.0:
+; SSE-NEXT:    testl %edx, %edx
+; SSE-NEXT:    jne .LBB0_1
+; SSE-NEXT:  # %bb.2:
+; SSE-NEXT:    movaps {{.*}}(%rip), %xmm0
+; SSE-NEXT:    movaps %xmm0, (%rsi)
+; SSE-NEXT:    retq
+; SSE-NEXT:  .LBB0_1:
+; SSE-NEXT:    movups (%rdi), %xmm0
+; SSE-NEXT:    movaps %xmm0, (%rsi)
+; SSE-NEXT:    retq
 ;
-; CHECK-LABEL: test_select:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    xorl %eax, %eax
-; CHECK-NEXT:    testl %edx, %edx
-; CHECK-NEXT:    cmovneq (%rdi), %rax
-; CHECK-NEXT:    movabsq $9223231299366420480, %rcx # imm = 0x7FFF800000000000
-; CHECK-NEXT:    cmovneq 8(%rdi), %rcx
-; CHECK-NEXT:    movq %rcx, 8(%rsi)
-; CHECK-NEXT:    movq %rax, (%rsi)
-; CHECK-NEXT:    retq
+; NOSSE-LABEL: test_select:
+; NOSSE:       # %bb.0:
+; NOSSE-NEXT:    xorl %eax, %eax
+; NOSSE-NEXT:    testl %edx, %edx
+; NOSSE-NEXT:    cmovneq (%rdi), %rax
+; NOSSE-NEXT:    movabsq $9223231299366420480, %rcx # imm = 0x7FFF800000000000
+; NOSSE-NEXT:    cmovneq 8(%rdi), %rcx
+; NOSSE-NEXT:    movq %rcx, 8(%rsi)
+; NOSSE-NEXT:    movq %rax, (%rsi)
+; NOSSE-NEXT:    retq
   %a = load fp128, fp128* %p, align 2
   %r = select i1 %c, fp128 %a, fp128 0xL00000000000000007FFF800000000000
   store fp128 %r, fp128* %q