summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen/X86/fmf-propagation.ll
diff options
context:
space:
mode:
authorMichael Berg <michael_c_berg@apple.com>2018-05-04 18:48:20 +0000
committerMichael Berg <michael_c_berg@apple.com>2018-05-04 18:48:20 +0000
commit7acc81b74428660efa5156815eebaee8a2ebe075 (patch)
tree43d5e80f2e186315ec3bdabe7635c905e792ae5c /llvm/test/CodeGen/X86/fmf-propagation.ll
parent0e51a125ea091955a1f5e7a7390a3b7953a3e314 (diff)
downloadbcm5719-llvm-7acc81b74428660efa5156815eebaee8a2ebe075.tar.gz
bcm5719-llvm-7acc81b74428660efa5156815eebaee8a2ebe075.zip
Fast Math Flag mapping into SDNode
Summary: Adding support for Fast flags in the SDNode to leverage fast math sub flag usage. Reviewers: spatel, arsenm, jbhateja, hfinkel, escha, qcolombet, echristo, wristow, javed.absar Reviewed By: spatel Subscribers: llvm-commits, rampitec, nhaehnle, tstellar, FarhanaAleen, nemanjai, javed.absar, jbhateja, hfinkel, wdng Differential Revision: https://reviews.llvm.org/D45710 llvm-svn: 331547
Diffstat (limited to 'llvm/test/CodeGen/X86/fmf-propagation.ll')
-rw-r--r--llvm/test/CodeGen/X86/fmf-propagation.ll8
1 files changed, 3 insertions, 5 deletions
diff --git a/llvm/test/CodeGen/X86/fmf-propagation.ll b/llvm/test/CodeGen/X86/fmf-propagation.ll
index 294a2952c76..56e813f371c 100644
--- a/llvm/test/CodeGen/X86/fmf-propagation.ll
+++ b/llvm/test/CodeGen/X86/fmf-propagation.ll
@@ -3,8 +3,6 @@
; This tests the propagation of fast-math-flags from IR instructions to SDNodeFlags.
-; FIXME: 'afn' and 'reassoc' were dropped. With 'fast', 'reassoc' got renamed to 'unsafe'.
-
; CHECK-LABEL: Initial selection DAG: %bb.0 'fmf_transfer:'
; CHECK: t5: f32 = fadd nsz t2, t4
@@ -12,9 +10,9 @@
; CHECK-NEXT: t7: f32 = fadd nnan t6, t4
; CHECK-NEXT: t8: f32 = fadd ninf t7, t4
; CHECK-NEXT: t9: f32 = fadd contract t8, t4
-; CHECK-NEXT: t10: f32 = fadd t9, t4
-; CHECK-NEXT: t11: f32 = fadd t10, t4
-; CHECK-NEXT: t12: f32 = fadd unsafe nnan ninf nsz arcp contract t11, t4
+; CHECK-NEXT: t10: f32 = fadd afn t9, t4
+; CHECK-NEXT: t11: f32 = fadd reassoc t10, t4
+; CHECK-NEXT: t12: f32 = fadd nnan ninf nsz arcp contract afn reassoc t11, t4
; CHECK: Optimized lowered selection DAG: %bb.0 'fmf_transfer:'
OpenPOWER on IntegriCloud