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authorSimon Pilgrim <llvm-dev@redking.me.uk>2018-09-19 18:59:08 +0000
committerSimon Pilgrim <llvm-dev@redking.me.uk>2018-09-19 18:59:08 +0000
commit2d0f20cc043458c945e4959c5b130c07a7f5b8b5 (patch)
tree4c6c2685582012433738444bea2cce36c82c7b04 /llvm/test/CodeGen/X86/fast-isel-shift.ll
parent894c39f770298e8972d3518c9b3531b59c819f56 (diff)
downloadbcm5719-llvm-2d0f20cc043458c945e4959c5b130c07a7f5b8b5.tar.gz
bcm5719-llvm-2d0f20cc043458c945e4959c5b130c07a7f5b8b5.zip
[X86] Handle COPYs of physregs better (regalloc hints)
Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
Diffstat (limited to 'llvm/test/CodeGen/X86/fast-isel-shift.ll')
-rw-r--r--llvm/test/CodeGen/X86/fast-isel-shift.ll112
1 files changed, 68 insertions, 44 deletions
diff --git a/llvm/test/CodeGen/X86/fast-isel-shift.ll b/llvm/test/CodeGen/X86/fast-isel-shift.ll
index 4dc56f351f5..2aff7cf51f8 100644
--- a/llvm/test/CodeGen/X86/fast-isel-shift.ll
+++ b/llvm/test/CodeGen/X86/fast-isel-shift.ll
@@ -5,8 +5,10 @@ define i8 @shl_i8(i8 %a, i8 %b) {
; CHECK-LABEL: shl_i8:
; CHECK: ## %bb.0:
; CHECK-NEXT: movl %esi, %ecx
-; CHECK-NEXT: shlb %cl, %dil
; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: ## kill: def $cl killed $cl killed $ecx
+; CHECK-NEXT: shlb %cl, %al
+; CHECK-NEXT: ## kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
%c = shl i8 %a, %b
ret i8 %c
@@ -16,9 +18,11 @@ define i16 @shl_i16(i16 %a, i16 %b) {
; CHECK-LABEL: shl_i16:
; CHECK: ## %bb.0:
; CHECK-NEXT: movl %esi, %ecx
-; CHECK-NEXT: ## kill: def $cl killed $cx
-; CHECK-NEXT: shlw %cl, %di
; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: ## kill: def $cx killed $cx killed $ecx
+; CHECK-NEXT: ## kill: def $cl killed $cx
+; CHECK-NEXT: shlw %cl, %ax
+; CHECK-NEXT: ## kill: def $ax killed $ax killed $eax
; CHECK-NEXT: retq
%c = shl i16 %a, %b
ret i16 %c
@@ -28,9 +32,9 @@ define i32 @shl_i32(i32 %a, i32 %b) {
; CHECK-LABEL: shl_i32:
; CHECK: ## %bb.0:
; CHECK-NEXT: movl %esi, %ecx
-; CHECK-NEXT: ## kill: def $cl killed $ecx
-; CHECK-NEXT: shll %cl, %edi
; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: ## kill: def $cl killed $ecx
+; CHECK-NEXT: shll %cl, %eax
; CHECK-NEXT: retq
%c = shl i32 %a, %b
ret i32 %c
@@ -40,9 +44,9 @@ define i64 @shl_i64(i64 %a, i64 %b) {
; CHECK-LABEL: shl_i64:
; CHECK: ## %bb.0:
; CHECK-NEXT: movq %rsi, %rcx
-; CHECK-NEXT: ## kill: def $cl killed $rcx
-; CHECK-NEXT: shlq %cl, %rdi
; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: ## kill: def $cl killed $rcx
+; CHECK-NEXT: shlq %cl, %rax
; CHECK-NEXT: retq
%c = shl i64 %a, %b
ret i64 %c
@@ -52,8 +56,10 @@ define i8 @lshr_i8(i8 %a, i8 %b) {
; CHECK-LABEL: lshr_i8:
; CHECK: ## %bb.0:
; CHECK-NEXT: movl %esi, %ecx
-; CHECK-NEXT: shrb %cl, %dil
; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: ## kill: def $cl killed $cl killed $ecx
+; CHECK-NEXT: shrb %cl, %al
+; CHECK-NEXT: ## kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
%c = lshr i8 %a, %b
ret i8 %c
@@ -63,9 +69,11 @@ define i16 @lshr_i16(i16 %a, i16 %b) {
; CHECK-LABEL: lshr_i16:
; CHECK: ## %bb.0:
; CHECK-NEXT: movl %esi, %ecx
-; CHECK-NEXT: ## kill: def $cl killed $cx
-; CHECK-NEXT: shrw %cl, %di
; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: ## kill: def $cx killed $cx killed $ecx
+; CHECK-NEXT: ## kill: def $cl killed $cx
+; CHECK-NEXT: shrw %cl, %ax
+; CHECK-NEXT: ## kill: def $ax killed $ax killed $eax
; CHECK-NEXT: retq
%c = lshr i16 %a, %b
ret i16 %c
@@ -75,9 +83,9 @@ define i32 @lshr_i32(i32 %a, i32 %b) {
; CHECK-LABEL: lshr_i32:
; CHECK: ## %bb.0:
; CHECK-NEXT: movl %esi, %ecx
-; CHECK-NEXT: ## kill: def $cl killed $ecx
-; CHECK-NEXT: shrl %cl, %edi
; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: ## kill: def $cl killed $ecx
+; CHECK-NEXT: shrl %cl, %eax
; CHECK-NEXT: retq
%c = lshr i32 %a, %b
ret i32 %c
@@ -87,9 +95,9 @@ define i64 @lshr_i64(i64 %a, i64 %b) {
; CHECK-LABEL: lshr_i64:
; CHECK: ## %bb.0:
; CHECK-NEXT: movq %rsi, %rcx
-; CHECK-NEXT: ## kill: def $cl killed $rcx
-; CHECK-NEXT: shrq %cl, %rdi
; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: ## kill: def $cl killed $rcx
+; CHECK-NEXT: shrq %cl, %rax
; CHECK-NEXT: retq
%c = lshr i64 %a, %b
ret i64 %c
@@ -99,8 +107,10 @@ define i8 @ashr_i8(i8 %a, i8 %b) {
; CHECK-LABEL: ashr_i8:
; CHECK: ## %bb.0:
; CHECK-NEXT: movl %esi, %ecx
-; CHECK-NEXT: sarb %cl, %dil
; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: ## kill: def $cl killed $cl killed $ecx
+; CHECK-NEXT: sarb %cl, %al
+; CHECK-NEXT: ## kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
%c = ashr i8 %a, %b
ret i8 %c
@@ -110,9 +120,11 @@ define i16 @ashr_i16(i16 %a, i16 %b) {
; CHECK-LABEL: ashr_i16:
; CHECK: ## %bb.0:
; CHECK-NEXT: movl %esi, %ecx
-; CHECK-NEXT: ## kill: def $cl killed $cx
-; CHECK-NEXT: sarw %cl, %di
; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: ## kill: def $cx killed $cx killed $ecx
+; CHECK-NEXT: ## kill: def $cl killed $cx
+; CHECK-NEXT: sarw %cl, %ax
+; CHECK-NEXT: ## kill: def $ax killed $ax killed $eax
; CHECK-NEXT: retq
%c = ashr i16 %a, %b
ret i16 %c
@@ -122,9 +134,9 @@ define i32 @ashr_i32(i32 %a, i32 %b) {
; CHECK-LABEL: ashr_i32:
; CHECK: ## %bb.0:
; CHECK-NEXT: movl %esi, %ecx
-; CHECK-NEXT: ## kill: def $cl killed $ecx
-; CHECK-NEXT: sarl %cl, %edi
; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: ## kill: def $cl killed $ecx
+; CHECK-NEXT: sarl %cl, %eax
; CHECK-NEXT: retq
%c = ashr i32 %a, %b
ret i32 %c
@@ -134,9 +146,9 @@ define i64 @ashr_i64(i64 %a, i64 %b) {
; CHECK-LABEL: ashr_i64:
; CHECK: ## %bb.0:
; CHECK-NEXT: movq %rsi, %rcx
-; CHECK-NEXT: ## kill: def $cl killed $rcx
-; CHECK-NEXT: sarq %cl, %rdi
; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: ## kill: def $cl killed $rcx
+; CHECK-NEXT: sarq %cl, %rax
; CHECK-NEXT: retq
%c = ashr i64 %a, %b
ret i64 %c
@@ -145,8 +157,9 @@ define i64 @ashr_i64(i64 %a, i64 %b) {
define i8 @shl_imm1_i8(i8 %a) {
; CHECK-LABEL: shl_imm1_i8:
; CHECK: ## %bb.0:
-; CHECK-NEXT: shlb $1, %dil
; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: shlb $1, %al
+; CHECK-NEXT: ## kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
%c = shl i8 %a, 1
ret i8 %c
@@ -185,8 +198,9 @@ define i64 @shl_imm1_i64(i64 %a) {
define i8 @lshr_imm1_i8(i8 %a) {
; CHECK-LABEL: lshr_imm1_i8:
; CHECK: ## %bb.0:
-; CHECK-NEXT: shrb $1, %dil
; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: shrb $1, %al
+; CHECK-NEXT: ## kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
%c = lshr i8 %a, 1
ret i8 %c
@@ -195,8 +209,9 @@ define i8 @lshr_imm1_i8(i8 %a) {
define i16 @lshr_imm1_i16(i16 %a) {
; CHECK-LABEL: lshr_imm1_i16:
; CHECK: ## %bb.0:
-; CHECK-NEXT: shrw $1, %di
; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: shrw $1, %ax
+; CHECK-NEXT: ## kill: def $ax killed $ax killed $eax
; CHECK-NEXT: retq
%c = lshr i16 %a, 1
ret i16 %c
@@ -205,8 +220,8 @@ define i16 @lshr_imm1_i16(i16 %a) {
define i32 @lshr_imm1_i32(i32 %a) {
; CHECK-LABEL: lshr_imm1_i32:
; CHECK: ## %bb.0:
-; CHECK-NEXT: shrl $1, %edi
; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: shrl $1, %eax
; CHECK-NEXT: retq
%c = lshr i32 %a, 1
ret i32 %c
@@ -215,8 +230,8 @@ define i32 @lshr_imm1_i32(i32 %a) {
define i64 @lshr_imm1_i64(i64 %a) {
; CHECK-LABEL: lshr_imm1_i64:
; CHECK: ## %bb.0:
-; CHECK-NEXT: shrq $1, %rdi
; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: shrq $1, %rax
; CHECK-NEXT: retq
%c = lshr i64 %a, 1
ret i64 %c
@@ -225,8 +240,9 @@ define i64 @lshr_imm1_i64(i64 %a) {
define i8 @ashr_imm1_i8(i8 %a) {
; CHECK-LABEL: ashr_imm1_i8:
; CHECK: ## %bb.0:
-; CHECK-NEXT: sarb $1, %dil
; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: sarb $1, %al
+; CHECK-NEXT: ## kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
%c = ashr i8 %a, 1
ret i8 %c
@@ -235,8 +251,9 @@ define i8 @ashr_imm1_i8(i8 %a) {
define i16 @ashr_imm1_i16(i16 %a) {
; CHECK-LABEL: ashr_imm1_i16:
; CHECK: ## %bb.0:
-; CHECK-NEXT: sarw $1, %di
; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: sarw $1, %ax
+; CHECK-NEXT: ## kill: def $ax killed $ax killed $eax
; CHECK-NEXT: retq
%c = ashr i16 %a, 1
ret i16 %c
@@ -245,8 +262,8 @@ define i16 @ashr_imm1_i16(i16 %a) {
define i32 @ashr_imm1_i32(i32 %a) {
; CHECK-LABEL: ashr_imm1_i32:
; CHECK: ## %bb.0:
-; CHECK-NEXT: sarl $1, %edi
; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: sarl $1, %eax
; CHECK-NEXT: retq
%c = ashr i32 %a, 1
ret i32 %c
@@ -255,8 +272,8 @@ define i32 @ashr_imm1_i32(i32 %a) {
define i64 @ashr_imm1_i64(i64 %a) {
; CHECK-LABEL: ashr_imm1_i64:
; CHECK: ## %bb.0:
-; CHECK-NEXT: sarq $1, %rdi
; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: sarq $1, %rax
; CHECK-NEXT: retq
%c = ashr i64 %a, 1
ret i64 %c
@@ -265,8 +282,9 @@ define i64 @ashr_imm1_i64(i64 %a) {
define i8 @shl_imm4_i8(i8 %a) {
; CHECK-LABEL: shl_imm4_i8:
; CHECK: ## %bb.0:
-; CHECK-NEXT: shlb $4, %dil
; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: shlb $4, %al
+; CHECK-NEXT: ## kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
%c = shl i8 %a, 4
ret i8 %c
@@ -275,8 +293,9 @@ define i8 @shl_imm4_i8(i8 %a) {
define i16 @shl_imm4_i16(i16 %a) {
; CHECK-LABEL: shl_imm4_i16:
; CHECK: ## %bb.0:
-; CHECK-NEXT: shlw $4, %di
; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: shlw $4, %ax
+; CHECK-NEXT: ## kill: def $ax killed $ax killed $eax
; CHECK-NEXT: retq
%c = shl i16 %a, 4
ret i16 %c
@@ -285,8 +304,8 @@ define i16 @shl_imm4_i16(i16 %a) {
define i32 @shl_imm4_i32(i32 %a) {
; CHECK-LABEL: shl_imm4_i32:
; CHECK: ## %bb.0:
-; CHECK-NEXT: shll $4, %edi
; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: shll $4, %eax
; CHECK-NEXT: retq
%c = shl i32 %a, 4
ret i32 %c
@@ -295,8 +314,8 @@ define i32 @shl_imm4_i32(i32 %a) {
define i64 @shl_imm4_i64(i64 %a) {
; CHECK-LABEL: shl_imm4_i64:
; CHECK: ## %bb.0:
-; CHECK-NEXT: shlq $4, %rdi
; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: shlq $4, %rax
; CHECK-NEXT: retq
%c = shl i64 %a, 4
ret i64 %c
@@ -305,8 +324,9 @@ define i64 @shl_imm4_i64(i64 %a) {
define i8 @lshr_imm4_i8(i8 %a) {
; CHECK-LABEL: lshr_imm4_i8:
; CHECK: ## %bb.0:
-; CHECK-NEXT: shrb $4, %dil
; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: shrb $4, %al
+; CHECK-NEXT: ## kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
%c = lshr i8 %a, 4
ret i8 %c
@@ -315,8 +335,9 @@ define i8 @lshr_imm4_i8(i8 %a) {
define i16 @lshr_imm4_i16(i16 %a) {
; CHECK-LABEL: lshr_imm4_i16:
; CHECK: ## %bb.0:
-; CHECK-NEXT: shrw $4, %di
; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: shrw $4, %ax
+; CHECK-NEXT: ## kill: def $ax killed $ax killed $eax
; CHECK-NEXT: retq
%c = lshr i16 %a, 4
ret i16 %c
@@ -325,8 +346,8 @@ define i16 @lshr_imm4_i16(i16 %a) {
define i32 @lshr_imm4_i32(i32 %a) {
; CHECK-LABEL: lshr_imm4_i32:
; CHECK: ## %bb.0:
-; CHECK-NEXT: shrl $4, %edi
; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: shrl $4, %eax
; CHECK-NEXT: retq
%c = lshr i32 %a, 4
ret i32 %c
@@ -335,8 +356,8 @@ define i32 @lshr_imm4_i32(i32 %a) {
define i64 @lshr_imm4_i64(i64 %a) {
; CHECK-LABEL: lshr_imm4_i64:
; CHECK: ## %bb.0:
-; CHECK-NEXT: shrq $4, %rdi
; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: shrq $4, %rax
; CHECK-NEXT: retq
%c = lshr i64 %a, 4
ret i64 %c
@@ -345,8 +366,9 @@ define i64 @lshr_imm4_i64(i64 %a) {
define i8 @ashr_imm4_i8(i8 %a) {
; CHECK-LABEL: ashr_imm4_i8:
; CHECK: ## %bb.0:
-; CHECK-NEXT: sarb $4, %dil
; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: sarb $4, %al
+; CHECK-NEXT: ## kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
%c = ashr i8 %a, 4
ret i8 %c
@@ -355,8 +377,9 @@ define i8 @ashr_imm4_i8(i8 %a) {
define i16 @ashr_imm4_i16(i16 %a) {
; CHECK-LABEL: ashr_imm4_i16:
; CHECK: ## %bb.0:
-; CHECK-NEXT: sarw $4, %di
; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: sarw $4, %ax
+; CHECK-NEXT: ## kill: def $ax killed $ax killed $eax
; CHECK-NEXT: retq
%c = ashr i16 %a, 4
ret i16 %c
@@ -365,8 +388,8 @@ define i16 @ashr_imm4_i16(i16 %a) {
define i32 @ashr_imm4_i32(i32 %a) {
; CHECK-LABEL: ashr_imm4_i32:
; CHECK: ## %bb.0:
-; CHECK-NEXT: sarl $4, %edi
; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: sarl $4, %eax
; CHECK-NEXT: retq
%c = ashr i32 %a, 4
ret i32 %c
@@ -375,8 +398,8 @@ define i32 @ashr_imm4_i32(i32 %a) {
define i64 @ashr_imm4_i64(i64 %a) {
; CHECK-LABEL: ashr_imm4_i64:
; CHECK: ## %bb.0:
-; CHECK-NEXT: sarq $4, %rdi
; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: sarq $4, %rax
; CHECK-NEXT: retq
%c = ashr i64 %a, 4
ret i64 %c
@@ -386,9 +409,10 @@ define i64 @ashr_imm4_i64(i64 %a) {
define i8 @PR36731(i8 %a) {
; CHECK-LABEL: PR36731:
; CHECK: ## %bb.0:
-; CHECK-NEXT: movb $255, %cl
-; CHECK-NEXT: shlb %cl, %dil
; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: movb $255, %cl
+; CHECK-NEXT: shlb %cl, %al
+; CHECK-NEXT: ## kill: def $al killed $al killed $eax
; CHECK-NEXT: retq
%b = shl i8 %a, -1
ret i8 %b
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