[CodeGen] Unify MBB reference format in both MIR and debug output

As part of the unification of the debug format and the MIR format, print
MBB references as '%bb.5'.

The MIR printer prints the IR name of a MBB only for block definitions.

* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g'
* find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g'
* grep -nr 'BB#' and fix

Differential Revision: https://reviews.llvm.org/D40422

llvm-svn: 319665

1 files changed, 48 insertions, 48 deletions

diff --git a/llvm/test/CodeGen/X86/fast-isel-select-pseudo-cmov.ll b/llvm/test/CodeGen/X86/fast-isel-select-pseudo-cmov.ll
index 8724b66c911..3ab040758fa 100644
--- a/llvm/test/CodeGen/X86/fast-isel-select-pseudo-cmov.ll
+++ b/llvm/test/CodeGen/X86/fast-isel-select-pseudo-cmov.ll
@@ -7,17 +7,17 @@
 
 define float @select_fcmp_one_f32(float %a, float %b, float %c, float %d) {
 ; SSE-LABEL: select_fcmp_one_f32:
-; SSE:       ## BB#0:
+; SSE:       ## %bb.0:
 ; SSE-NEXT:    ucomiss %xmm1, %xmm0
 ; SSE-NEXT:    jne LBB0_2
-; SSE-NEXT:  ## BB#1:
+; SSE-NEXT:  ## %bb.1:
 ; SSE-NEXT:    movaps %xmm3, %xmm2
 ; SSE-NEXT:  LBB0_2:
 ; SSE-NEXT:    movaps %xmm2, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: select_fcmp_one_f32:
-; AVX:       ## BB#0:
+; AVX:       ## %bb.0:
 ; AVX-NEXT:    vcmpneq_oqss %xmm1, %xmm0, %xmm0
 ; AVX-NEXT:    vblendvps %xmm0, %xmm2, %xmm3, %xmm0
 ; AVX-NEXT:    retq
@@ -28,17 +28,17 @@ define float @select_fcmp_one_f32(float %a, float %b, float %c, float %d) {
 
 define double @select_fcmp_one_f64(double %a, double %b, double %c, double %d) {
 ; SSE-LABEL: select_fcmp_one_f64:
-; SSE:       ## BB#0:
+; SSE:       ## %bb.0:
 ; SSE-NEXT:    ucomisd %xmm1, %xmm0
 ; SSE-NEXT:    jne LBB1_2
-; SSE-NEXT:  ## BB#1:
+; SSE-NEXT:  ## %bb.1:
 ; SSE-NEXT:    movaps %xmm3, %xmm2
 ; SSE-NEXT:  LBB1_2:
 ; SSE-NEXT:    movaps %xmm2, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: select_fcmp_one_f64:
-; AVX:       ## BB#0:
+; AVX:       ## %bb.0:
 ; AVX-NEXT:    vcmpneq_oqsd %xmm1, %xmm0, %xmm0
 ; AVX-NEXT:    vblendvpd %xmm0, %xmm2, %xmm3, %xmm0
 ; AVX-NEXT:    retq
@@ -49,19 +49,19 @@ define double @select_fcmp_one_f64(double %a, double %b, double %c, double %d) {
 
 define float @select_icmp_eq_f32(i64 %a, i64 %b, float %c, float %d) {
 ; SSE-LABEL: select_icmp_eq_f32:
-; SSE:       ## BB#0:
+; SSE:       ## %bb.0:
 ; SSE-NEXT:    cmpq %rsi, %rdi
 ; SSE-NEXT:    je LBB2_2
-; SSE-NEXT:  ## BB#1:
+; SSE-NEXT:  ## %bb.1:
 ; SSE-NEXT:    movaps %xmm1, %xmm0
 ; SSE-NEXT:  LBB2_2:
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: select_icmp_eq_f32:
-; AVX:       ## BB#0:
+; AVX:       ## %bb.0:
 ; AVX-NEXT:    cmpq %rsi, %rdi
 ; AVX-NEXT:    je LBB2_2
-; AVX-NEXT:  ## BB#1:
+; AVX-NEXT:  ## %bb.1:
 ; AVX-NEXT:    vmovaps %xmm1, %xmm0
 ; AVX-NEXT:  LBB2_2:
 ; AVX-NEXT:    retq
@@ -72,19 +72,19 @@ define float @select_icmp_eq_f32(i64 %a, i64 %b, float %c, float %d) {
 
 define float @select_icmp_ne_f32(i64 %a, i64 %b, float %c, float %d) {
 ; SSE-LABEL: select_icmp_ne_f32:
-; SSE:       ## BB#0:
+; SSE:       ## %bb.0:
 ; SSE-NEXT:    cmpq %rsi, %rdi
 ; SSE-NEXT:    jne LBB3_2
-; SSE-NEXT:  ## BB#1:
+; SSE-NEXT:  ## %bb.1:
 ; SSE-NEXT:    movaps %xmm1, %xmm0
 ; SSE-NEXT:  LBB3_2:
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: select_icmp_ne_f32:
-; AVX:       ## BB#0:
+; AVX:       ## %bb.0:
 ; AVX-NEXT:    cmpq %rsi, %rdi
 ; AVX-NEXT:    jne LBB3_2
-; AVX-NEXT:  ## BB#1:
+; AVX-NEXT:  ## %bb.1:
 ; AVX-NEXT:    vmovaps %xmm1, %xmm0
 ; AVX-NEXT:  LBB3_2:
 ; AVX-NEXT:    retq
@@ -95,19 +95,19 @@ define float @select_icmp_ne_f32(i64 %a, i64 %b, float %c, float %d) {
 
 define float @select_icmp_ugt_f32(i64 %a, i64 %b, float %c, float %d) {
 ; SSE-LABEL: select_icmp_ugt_f32:
-; SSE:       ## BB#0:
+; SSE:       ## %bb.0:
 ; SSE-NEXT:    cmpq %rsi, %rdi
 ; SSE-NEXT:    ja LBB4_2
-; SSE-NEXT:  ## BB#1:
+; SSE-NEXT:  ## %bb.1:
 ; SSE-NEXT:    movaps %xmm1, %xmm0
 ; SSE-NEXT:  LBB4_2:
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: select_icmp_ugt_f32:
-; AVX:       ## BB#0:
+; AVX:       ## %bb.0:
 ; AVX-NEXT:    cmpq %rsi, %rdi
 ; AVX-NEXT:    ja LBB4_2
-; AVX-NEXT:  ## BB#1:
+; AVX-NEXT:  ## %bb.1:
 ; AVX-NEXT:    vmovaps %xmm1, %xmm0
 ; AVX-NEXT:  LBB4_2:
 ; AVX-NEXT:    retq
@@ -118,19 +118,19 @@ define float @select_icmp_ugt_f32(i64 %a, i64 %b, float %c, float %d) {
 
 define float @select_icmp_uge_f32(i64 %a, i64 %b, float %c, float %d) {
 ; SSE-LABEL: select_icmp_uge_f32:
-; SSE:       ## BB#0:
+; SSE:       ## %bb.0:
 ; SSE-NEXT:    cmpq %rsi, %rdi
 ; SSE-NEXT:    jae LBB5_2
-; SSE-NEXT:  ## BB#1:
+; SSE-NEXT:  ## %bb.1:
 ; SSE-NEXT:    movaps %xmm1, %xmm0
 ; SSE-NEXT:  LBB5_2:
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: select_icmp_uge_f32:
-; AVX:       ## BB#0:
+; AVX:       ## %bb.0:
 ; AVX-NEXT:    cmpq %rsi, %rdi
 ; AVX-NEXT:    jae LBB5_2
-; AVX-NEXT:  ## BB#1:
+; AVX-NEXT:  ## %bb.1:
 ; AVX-NEXT:    vmovaps %xmm1, %xmm0
 ; AVX-NEXT:  LBB5_2:
 ; AVX-NEXT:    retq
@@ -141,19 +141,19 @@ define float @select_icmp_uge_f32(i64 %a, i64 %b, float %c, float %d) {
 
 define float @select_icmp_ult_f32(i64 %a, i64 %b, float %c, float %d) {
 ; SSE-LABEL: select_icmp_ult_f32:
-; SSE:       ## BB#0:
+; SSE:       ## %bb.0:
 ; SSE-NEXT:    cmpq %rsi, %rdi
 ; SSE-NEXT:    jb LBB6_2
-; SSE-NEXT:  ## BB#1:
+; SSE-NEXT:  ## %bb.1:
 ; SSE-NEXT:    movaps %xmm1, %xmm0
 ; SSE-NEXT:  LBB6_2:
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: select_icmp_ult_f32:
-; AVX:       ## BB#0:
+; AVX:       ## %bb.0:
 ; AVX-NEXT:    cmpq %rsi, %rdi
 ; AVX-NEXT:    jb LBB6_2
-; AVX-NEXT:  ## BB#1:
+; AVX-NEXT:  ## %bb.1:
 ; AVX-NEXT:    vmovaps %xmm1, %xmm0
 ; AVX-NEXT:  LBB6_2:
 ; AVX-NEXT:    retq
@@ -164,19 +164,19 @@ define float @select_icmp_ult_f32(i64 %a, i64 %b, float %c, float %d) {
 
 define float @select_icmp_ule_f32(i64 %a, i64 %b, float %c, float %d) {
 ; SSE-LABEL: select_icmp_ule_f32:
-; SSE:       ## BB#0:
+; SSE:       ## %bb.0:
 ; SSE-NEXT:    cmpq %rsi, %rdi
 ; SSE-NEXT:    jbe LBB7_2
-; SSE-NEXT:  ## BB#1:
+; SSE-NEXT:  ## %bb.1:
 ; SSE-NEXT:    movaps %xmm1, %xmm0
 ; SSE-NEXT:  LBB7_2:
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: select_icmp_ule_f32:
-; AVX:       ## BB#0:
+; AVX:       ## %bb.0:
 ; AVX-NEXT:    cmpq %rsi, %rdi
 ; AVX-NEXT:    jbe LBB7_2
-; AVX-NEXT:  ## BB#1:
+; AVX-NEXT:  ## %bb.1:
 ; AVX-NEXT:    vmovaps %xmm1, %xmm0
 ; AVX-NEXT:  LBB7_2:
 ; AVX-NEXT:    retq
@@ -187,19 +187,19 @@ define float @select_icmp_ule_f32(i64 %a, i64 %b, float %c, float %d) {
 
 define float @select_icmp_sgt_f32(i64 %a, i64 %b, float %c, float %d) {
 ; SSE-LABEL: select_icmp_sgt_f32:
-; SSE:       ## BB#0:
+; SSE:       ## %bb.0:
 ; SSE-NEXT:    cmpq %rsi, %rdi
 ; SSE-NEXT:    jg LBB8_2
-; SSE-NEXT:  ## BB#1:
+; SSE-NEXT:  ## %bb.1:
 ; SSE-NEXT:    movaps %xmm1, %xmm0
 ; SSE-NEXT:  LBB8_2:
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: select_icmp_sgt_f32:
-; AVX:       ## BB#0:
+; AVX:       ## %bb.0:
 ; AVX-NEXT:    cmpq %rsi, %rdi
 ; AVX-NEXT:    jg LBB8_2
-; AVX-NEXT:  ## BB#1:
+; AVX-NEXT:  ## %bb.1:
 ; AVX-NEXT:    vmovaps %xmm1, %xmm0
 ; AVX-NEXT:  LBB8_2:
 ; AVX-NEXT:    retq
@@ -210,19 +210,19 @@ define float @select_icmp_sgt_f32(i64 %a, i64 %b, float %c, float %d) {
 
 define float @select_icmp_sge_f32(i64 %a, i64 %b, float %c, float %d) {
 ; SSE-LABEL: select_icmp_sge_f32:
-; SSE:       ## BB#0:
+; SSE:       ## %bb.0:
 ; SSE-NEXT:    cmpq %rsi, %rdi
 ; SSE-NEXT:    jge LBB9_2
-; SSE-NEXT:  ## BB#1:
+; SSE-NEXT:  ## %bb.1:
 ; SSE-NEXT:    movaps %xmm1, %xmm0
 ; SSE-NEXT:  LBB9_2:
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: select_icmp_sge_f32:
-; AVX:       ## BB#0:
+; AVX:       ## %bb.0:
 ; AVX-NEXT:    cmpq %rsi, %rdi
 ; AVX-NEXT:    jge LBB9_2
-; AVX-NEXT:  ## BB#1:
+; AVX-NEXT:  ## %bb.1:
 ; AVX-NEXT:    vmovaps %xmm1, %xmm0
 ; AVX-NEXT:  LBB9_2:
 ; AVX-NEXT:    retq
@@ -233,19 +233,19 @@ define float @select_icmp_sge_f32(i64 %a, i64 %b, float %c, float %d) {
 
 define float @select_icmp_slt_f32(i64 %a, i64 %b, float %c, float %d) {
 ; SSE-LABEL: select_icmp_slt_f32:
-; SSE:       ## BB#0:
+; SSE:       ## %bb.0:
 ; SSE-NEXT:    cmpq %rsi, %rdi
 ; SSE-NEXT:    jl LBB10_2
-; SSE-NEXT:  ## BB#1:
+; SSE-NEXT:  ## %bb.1:
 ; SSE-NEXT:    movaps %xmm1, %xmm0
 ; SSE-NEXT:  LBB10_2:
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: select_icmp_slt_f32:
-; AVX:       ## BB#0:
+; AVX:       ## %bb.0:
 ; AVX-NEXT:    cmpq %rsi, %rdi
 ; AVX-NEXT:    jl LBB10_2
-; AVX-NEXT:  ## BB#1:
+; AVX-NEXT:  ## %bb.1:
 ; AVX-NEXT:    vmovaps %xmm1, %xmm0
 ; AVX-NEXT:  LBB10_2:
 ; AVX-NEXT:    retq
@@ -256,19 +256,19 @@ define float @select_icmp_slt_f32(i64 %a, i64 %b, float %c, float %d) {
 
 define float @select_icmp_sle_f32(i64 %a, i64 %b, float %c, float %d) {
 ; SSE-LABEL: select_icmp_sle_f32:
-; SSE:       ## BB#0:
+; SSE:       ## %bb.0:
 ; SSE-NEXT:    cmpq %rsi, %rdi
 ; SSE-NEXT:    jle LBB11_2
-; SSE-NEXT:  ## BB#1:
+; SSE-NEXT:  ## %bb.1:
 ; SSE-NEXT:    movaps %xmm1, %xmm0
 ; SSE-NEXT:  LBB11_2:
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: select_icmp_sle_f32:
-; AVX:       ## BB#0:
+; AVX:       ## %bb.0:
 ; AVX-NEXT:    cmpq %rsi, %rdi
 ; AVX-NEXT:    jle LBB11_2
-; AVX-NEXT:  ## BB#1:
+; AVX-NEXT:  ## %bb.1:
 ; AVX-NEXT:    vmovaps %xmm1, %xmm0
 ; AVX-NEXT:  LBB11_2:
 ; AVX-NEXT:    retq
@@ -279,10 +279,10 @@ define float @select_icmp_sle_f32(i64 %a, i64 %b, float %c, float %d) {
 
 define i8 @select_icmp_sle_i8(i64 %a, i64 %b, i8 %c, i8 %d) {
 ; CHECK-LABEL: select_icmp_sle_i8:
-; CHECK:       ## BB#0:
+; CHECK:       ## %bb.0:
 ; CHECK-NEXT:    cmpq %rsi, %rdi
 ; CHECK-NEXT:    jle LBB12_2
-; CHECK-NEXT:  ## BB#1:
+; CHECK-NEXT:  ## %bb.1:
 ; CHECK-NEXT:    movl %ecx, %edx
 ; CHECK-NEXT:  LBB12_2:
 ; CHECK-NEXT:    movl %edx, %eax