[X86] Handle COPYs of physregs better (regalloc hints)

Enable enableMultipleCopyHints() on X86.

Original Patch by @jonpa:

While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling.

Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates.

Differential Revision: https://reviews.llvm.org/D38128

llvm-svn: 342578

1 files changed, 94 insertions, 94 deletions

diff --git a/llvm/test/CodeGen/X86/fast-isel-select-cmov2.ll b/llvm/test/CodeGen/X86/fast-isel-select-cmov2.ll
index 3dd4d2b3433..eb2bd08a2b1 100644
--- a/llvm/test/CodeGen/X86/fast-isel-select-cmov2.ll
+++ b/llvm/test/CodeGen/X86/fast-isel-select-cmov2.ll
@@ -19,30 +19,30 @@ define i64 @select_fcmp_false_cmov(double %a, double %b, i64 %c, i64 %d) {
 define i64 @select_fcmp_oeq_cmov(double %a, double %b, i64 %c, i64 %d) {
 ; SDAG-LABEL: select_fcmp_oeq_cmov:
 ; SDAG:       ## %bb.0:
-; SDAG-NEXT:    ucomisd %xmm1, %xmm0
-; SDAG-NEXT:    cmovneq %rsi, %rdi
-; SDAG-NEXT:    cmovpq %rsi, %rdi
 ; SDAG-NEXT:    movq %rdi, %rax
+; SDAG-NEXT:    ucomisd %xmm1, %xmm0
+; SDAG-NEXT:    cmovneq %rsi, %rax
+; SDAG-NEXT:    cmovpq %rsi, %rax
 ; SDAG-NEXT:    retq
 ;
 ; FAST-LABEL: select_fcmp_oeq_cmov:
 ; FAST:       ## %bb.0:
-; FAST-NEXT:    ucomisd %xmm1, %xmm0
-; FAST-NEXT:    setnp %al
-; FAST-NEXT:    sete %cl
-; FAST-NEXT:    testb %al, %cl
-; FAST-NEXT:    cmoveq %rsi, %rdi
 ; FAST-NEXT:    movq %rdi, %rax
+; FAST-NEXT:    ucomisd %xmm1, %xmm0
+; FAST-NEXT:    setnp %cl
+; FAST-NEXT:    sete %dl
+; FAST-NEXT:    testb %cl, %dl
+; FAST-NEXT:    cmoveq %rsi, %rax
 ; FAST-NEXT:    retq
 ;
 ; FAST_AVX-LABEL: select_fcmp_oeq_cmov:
 ; FAST_AVX:       ## %bb.0:
-; FAST_AVX-NEXT:    vucomisd %xmm1, %xmm0
-; FAST_AVX-NEXT:    setnp %al
-; FAST_AVX-NEXT:    sete %cl
-; FAST_AVX-NEXT:    testb %al, %cl
-; FAST_AVX-NEXT:    cmoveq %rsi, %rdi
 ; FAST_AVX-NEXT:    movq %rdi, %rax
+; FAST_AVX-NEXT:    vucomisd %xmm1, %xmm0
+; FAST_AVX-NEXT:    setnp %cl
+; FAST_AVX-NEXT:    sete %dl
+; FAST_AVX-NEXT:    testb %cl, %dl
+; FAST_AVX-NEXT:    cmoveq %rsi, %rax
 ; FAST_AVX-NEXT:    retq
   %1 = fcmp oeq double %a, %b
   %2 = select i1 %1, i64 %c, i64 %d
@@ -52,16 +52,16 @@ define i64 @select_fcmp_oeq_cmov(double %a, double %b, i64 %c, i64 %d) {
 define i64 @select_fcmp_ogt_cmov(double %a, double %b, i64 %c, i64 %d) {
 ; NOAVX-LABEL: select_fcmp_ogt_cmov:
 ; NOAVX:       ## %bb.0:
-; NOAVX-NEXT:    ucomisd %xmm1, %xmm0
-; NOAVX-NEXT:    cmovbeq %rsi, %rdi
 ; NOAVX-NEXT:    movq %rdi, %rax
+; NOAVX-NEXT:    ucomisd %xmm1, %xmm0
+; NOAVX-NEXT:    cmovbeq %rsi, %rax
 ; NOAVX-NEXT:    retq
 ;
 ; FAST_AVX-LABEL: select_fcmp_ogt_cmov:
 ; FAST_AVX:       ## %bb.0:
-; FAST_AVX-NEXT:    vucomisd %xmm1, %xmm0
-; FAST_AVX-NEXT:    cmovbeq %rsi, %rdi
 ; FAST_AVX-NEXT:    movq %rdi, %rax
+; FAST_AVX-NEXT:    vucomisd %xmm1, %xmm0
+; FAST_AVX-NEXT:    cmovbeq %rsi, %rax
 ; FAST_AVX-NEXT:    retq
   %1 = fcmp ogt double %a, %b
   %2 = select i1 %1, i64 %c, i64 %d
@@ -71,16 +71,16 @@ define i64 @select_fcmp_ogt_cmov(double %a, double %b, i64 %c, i64 %d) {
 define i64 @select_fcmp_oge_cmov(double %a, double %b, i64 %c, i64 %d) {
 ; NOAVX-LABEL: select_fcmp_oge_cmov:
 ; NOAVX:       ## %bb.0:
-; NOAVX-NEXT:    ucomisd %xmm1, %xmm0
-; NOAVX-NEXT:    cmovbq %rsi, %rdi
 ; NOAVX-NEXT:    movq %rdi, %rax
+; NOAVX-NEXT:    ucomisd %xmm1, %xmm0
+; NOAVX-NEXT:    cmovbq %rsi, %rax
 ; NOAVX-NEXT:    retq
 ;
 ; FAST_AVX-LABEL: select_fcmp_oge_cmov:
 ; FAST_AVX:       ## %bb.0:
-; FAST_AVX-NEXT:    vucomisd %xmm1, %xmm0
-; FAST_AVX-NEXT:    cmovbq %rsi, %rdi
 ; FAST_AVX-NEXT:    movq %rdi, %rax
+; FAST_AVX-NEXT:    vucomisd %xmm1, %xmm0
+; FAST_AVX-NEXT:    cmovbq %rsi, %rax
 ; FAST_AVX-NEXT:    retq
   %1 = fcmp oge double %a, %b
   %2 = select i1 %1, i64 %c, i64 %d
@@ -90,16 +90,16 @@ define i64 @select_fcmp_oge_cmov(double %a, double %b, i64 %c, i64 %d) {
 define i64 @select_fcmp_olt_cmov(double %a, double %b, i64 %c, i64 %d) {
 ; NOAVX-LABEL: select_fcmp_olt_cmov:
 ; NOAVX:       ## %bb.0:
-; NOAVX-NEXT:    ucomisd %xmm0, %xmm1
-; NOAVX-NEXT:    cmovbeq %rsi, %rdi
 ; NOAVX-NEXT:    movq %rdi, %rax
+; NOAVX-NEXT:    ucomisd %xmm0, %xmm1
+; NOAVX-NEXT:    cmovbeq %rsi, %rax
 ; NOAVX-NEXT:    retq
 ;
 ; FAST_AVX-LABEL: select_fcmp_olt_cmov:
 ; FAST_AVX:       ## %bb.0:
-; FAST_AVX-NEXT:    vucomisd %xmm0, %xmm1
-; FAST_AVX-NEXT:    cmovbeq %rsi, %rdi
 ; FAST_AVX-NEXT:    movq %rdi, %rax
+; FAST_AVX-NEXT:    vucomisd %xmm0, %xmm1
+; FAST_AVX-NEXT:    cmovbeq %rsi, %rax
 ; FAST_AVX-NEXT:    retq
   %1 = fcmp olt double %a, %b
   %2 = select i1 %1, i64 %c, i64 %d
@@ -109,16 +109,16 @@ define i64 @select_fcmp_olt_cmov(double %a, double %b, i64 %c, i64 %d) {
 define i64 @select_fcmp_ole_cmov(double %a, double %b, i64 %c, i64 %d) {
 ; NOAVX-LABEL: select_fcmp_ole_cmov:
 ; NOAVX:       ## %bb.0:
-; NOAVX-NEXT:    ucomisd %xmm0, %xmm1
-; NOAVX-NEXT:    cmovbq %rsi, %rdi
 ; NOAVX-NEXT:    movq %rdi, %rax
+; NOAVX-NEXT:    ucomisd %xmm0, %xmm1
+; NOAVX-NEXT:    cmovbq %rsi, %rax
 ; NOAVX-NEXT:    retq
 ;
 ; FAST_AVX-LABEL: select_fcmp_ole_cmov:
 ; FAST_AVX:       ## %bb.0:
-; FAST_AVX-NEXT:    vucomisd %xmm0, %xmm1
-; FAST_AVX-NEXT:    cmovbq %rsi, %rdi
 ; FAST_AVX-NEXT:    movq %rdi, %rax
+; FAST_AVX-NEXT:    vucomisd %xmm0, %xmm1
+; FAST_AVX-NEXT:    cmovbq %rsi, %rax
 ; FAST_AVX-NEXT:    retq
   %1 = fcmp ole double %a, %b
   %2 = select i1 %1, i64 %c, i64 %d
@@ -128,16 +128,16 @@ define i64 @select_fcmp_ole_cmov(double %a, double %b, i64 %c, i64 %d) {
 define i64 @select_fcmp_one_cmov(double %a, double %b, i64 %c, i64 %d) {
 ; NOAVX-LABEL: select_fcmp_one_cmov:
 ; NOAVX:       ## %bb.0:
-; NOAVX-NEXT:    ucomisd %xmm1, %xmm0
-; NOAVX-NEXT:    cmoveq %rsi, %rdi
 ; NOAVX-NEXT:    movq %rdi, %rax
+; NOAVX-NEXT:    ucomisd %xmm1, %xmm0
+; NOAVX-NEXT:    cmoveq %rsi, %rax
 ; NOAVX-NEXT:    retq
 ;
 ; FAST_AVX-LABEL: select_fcmp_one_cmov:
 ; FAST_AVX:       ## %bb.0:
-; FAST_AVX-NEXT:    vucomisd %xmm1, %xmm0
-; FAST_AVX-NEXT:    cmoveq %rsi, %rdi
 ; FAST_AVX-NEXT:    movq %rdi, %rax
+; FAST_AVX-NEXT:    vucomisd %xmm1, %xmm0
+; FAST_AVX-NEXT:    cmoveq %rsi, %rax
 ; FAST_AVX-NEXT:    retq
   %1 = fcmp one double %a, %b
   %2 = select i1 %1, i64 %c, i64 %d
@@ -147,16 +147,16 @@ define i64 @select_fcmp_one_cmov(double %a, double %b, i64 %c, i64 %d) {
 define i64 @select_fcmp_ord_cmov(double %a, double %b, i64 %c, i64 %d) {
 ; NOAVX-LABEL: select_fcmp_ord_cmov:
 ; NOAVX:       ## %bb.0:
-; NOAVX-NEXT:    ucomisd %xmm1, %xmm0
-; NOAVX-NEXT:    cmovpq %rsi, %rdi
 ; NOAVX-NEXT:    movq %rdi, %rax
+; NOAVX-NEXT:    ucomisd %xmm1, %xmm0
+; NOAVX-NEXT:    cmovpq %rsi, %rax
 ; NOAVX-NEXT:    retq
 ;
 ; FAST_AVX-LABEL: select_fcmp_ord_cmov:
 ; FAST_AVX:       ## %bb.0:
-; FAST_AVX-NEXT:    vucomisd %xmm1, %xmm0
-; FAST_AVX-NEXT:    cmovpq %rsi, %rdi
 ; FAST_AVX-NEXT:    movq %rdi, %rax
+; FAST_AVX-NEXT:    vucomisd %xmm1, %xmm0
+; FAST_AVX-NEXT:    cmovpq %rsi, %rax
 ; FAST_AVX-NEXT:    retq
   %1 = fcmp ord double %a, %b
   %2 = select i1 %1, i64 %c, i64 %d
@@ -166,16 +166,16 @@ define i64 @select_fcmp_ord_cmov(double %a, double %b, i64 %c, i64 %d) {
 define i64 @select_fcmp_uno_cmov(double %a, double %b, i64 %c, i64 %d) {
 ; NOAVX-LABEL: select_fcmp_uno_cmov:
 ; NOAVX:       ## %bb.0:
-; NOAVX-NEXT:    ucomisd %xmm1, %xmm0
-; NOAVX-NEXT:    cmovnpq %rsi, %rdi
 ; NOAVX-NEXT:    movq %rdi, %rax
+; NOAVX-NEXT:    ucomisd %xmm1, %xmm0
+; NOAVX-NEXT:    cmovnpq %rsi, %rax
 ; NOAVX-NEXT:    retq
 ;
 ; FAST_AVX-LABEL: select_fcmp_uno_cmov:
 ; FAST_AVX:       ## %bb.0:
-; FAST_AVX-NEXT:    vucomisd %xmm1, %xmm0
-; FAST_AVX-NEXT:    cmovnpq %rsi, %rdi
 ; FAST_AVX-NEXT:    movq %rdi, %rax
+; FAST_AVX-NEXT:    vucomisd %xmm1, %xmm0
+; FAST_AVX-NEXT:    cmovnpq %rsi, %rax
 ; FAST_AVX-NEXT:    retq
   %1 = fcmp uno double %a, %b
   %2 = select i1 %1, i64 %c, i64 %d
@@ -185,16 +185,16 @@ define i64 @select_fcmp_uno_cmov(double %a, double %b, i64 %c, i64 %d) {
 define i64 @select_fcmp_ueq_cmov(double %a, double %b, i64 %c, i64 %d) {
 ; NOAVX-LABEL: select_fcmp_ueq_cmov:
 ; NOAVX:       ## %bb.0:
-; NOAVX-NEXT:    ucomisd %xmm1, %xmm0
-; NOAVX-NEXT:    cmovneq %rsi, %rdi
 ; NOAVX-NEXT:    movq %rdi, %rax
+; NOAVX-NEXT:    ucomisd %xmm1, %xmm0
+; NOAVX-NEXT:    cmovneq %rsi, %rax
 ; NOAVX-NEXT:    retq
 ;
 ; FAST_AVX-LABEL: select_fcmp_ueq_cmov:
 ; FAST_AVX:       ## %bb.0:
-; FAST_AVX-NEXT:    vucomisd %xmm1, %xmm0
-; FAST_AVX-NEXT:    cmovneq %rsi, %rdi
 ; FAST_AVX-NEXT:    movq %rdi, %rax
+; FAST_AVX-NEXT:    vucomisd %xmm1, %xmm0
+; FAST_AVX-NEXT:    cmovneq %rsi, %rax
 ; FAST_AVX-NEXT:    retq
   %1 = fcmp ueq double %a, %b
   %2 = select i1 %1, i64 %c, i64 %d
@@ -204,16 +204,16 @@ define i64 @select_fcmp_ueq_cmov(double %a, double %b, i64 %c, i64 %d) {
 define i64 @select_fcmp_ugt_cmov(double %a, double %b, i64 %c, i64 %d) {
 ; NOAVX-LABEL: select_fcmp_ugt_cmov:
 ; NOAVX:       ## %bb.0:
-; NOAVX-NEXT:    ucomisd %xmm0, %xmm1
-; NOAVX-NEXT:    cmovaeq %rsi, %rdi
 ; NOAVX-NEXT:    movq %rdi, %rax
+; NOAVX-NEXT:    ucomisd %xmm0, %xmm1
+; NOAVX-NEXT:    cmovaeq %rsi, %rax
 ; NOAVX-NEXT:    retq
 ;
 ; FAST_AVX-LABEL: select_fcmp_ugt_cmov:
 ; FAST_AVX:       ## %bb.0:
-; FAST_AVX-NEXT:    vucomisd %xmm0, %xmm1
-; FAST_AVX-NEXT:    cmovaeq %rsi, %rdi
 ; FAST_AVX-NEXT:    movq %rdi, %rax
+; FAST_AVX-NEXT:    vucomisd %xmm0, %xmm1
+; FAST_AVX-NEXT:    cmovaeq %rsi, %rax
 ; FAST_AVX-NEXT:    retq
   %1 = fcmp ugt double %a, %b
   %2 = select i1 %1, i64 %c, i64 %d
@@ -223,16 +223,16 @@ define i64 @select_fcmp_ugt_cmov(double %a, double %b, i64 %c, i64 %d) {
 define i64 @select_fcmp_uge_cmov(double %a, double %b, i64 %c, i64 %d) {
 ; NOAVX-LABEL: select_fcmp_uge_cmov:
 ; NOAVX:       ## %bb.0:
-; NOAVX-NEXT:    ucomisd %xmm0, %xmm1
-; NOAVX-NEXT:    cmovaq %rsi, %rdi
 ; NOAVX-NEXT:    movq %rdi, %rax
+; NOAVX-NEXT:    ucomisd %xmm0, %xmm1
+; NOAVX-NEXT:    cmovaq %rsi, %rax
 ; NOAVX-NEXT:    retq
 ;
 ; FAST_AVX-LABEL: select_fcmp_uge_cmov:
 ; FAST_AVX:       ## %bb.0:
-; FAST_AVX-NEXT:    vucomisd %xmm0, %xmm1
-; FAST_AVX-NEXT:    cmovaq %rsi, %rdi
 ; FAST_AVX-NEXT:    movq %rdi, %rax
+; FAST_AVX-NEXT:    vucomisd %xmm0, %xmm1
+; FAST_AVX-NEXT:    cmovaq %rsi, %rax
 ; FAST_AVX-NEXT:    retq
   %1 = fcmp uge double %a, %b
   %2 = select i1 %1, i64 %c, i64 %d
@@ -242,16 +242,16 @@ define i64 @select_fcmp_uge_cmov(double %a, double %b, i64 %c, i64 %d) {
 define i64 @select_fcmp_ult_cmov(double %a, double %b, i64 %c, i64 %d) {
 ; NOAVX-LABEL: select_fcmp_ult_cmov:
 ; NOAVX:       ## %bb.0:
-; NOAVX-NEXT:    ucomisd %xmm1, %xmm0
-; NOAVX-NEXT:    cmovaeq %rsi, %rdi
 ; NOAVX-NEXT:    movq %rdi, %rax
+; NOAVX-NEXT:    ucomisd %xmm1, %xmm0
+; NOAVX-NEXT:    cmovaeq %rsi, %rax
 ; NOAVX-NEXT:    retq
 ;
 ; FAST_AVX-LABEL: select_fcmp_ult_cmov:
 ; FAST_AVX:       ## %bb.0:
-; FAST_AVX-NEXT:    vucomisd %xmm1, %xmm0
-; FAST_AVX-NEXT:    cmovaeq %rsi, %rdi
 ; FAST_AVX-NEXT:    movq %rdi, %rax
+; FAST_AVX-NEXT:    vucomisd %xmm1, %xmm0
+; FAST_AVX-NEXT:    cmovaeq %rsi, %rax
 ; FAST_AVX-NEXT:    retq
   %1 = fcmp ult double %a, %b
   %2 = select i1 %1, i64 %c, i64 %d
@@ -261,16 +261,16 @@ define i64 @select_fcmp_ult_cmov(double %a, double %b, i64 %c, i64 %d) {
 define i64 @select_fcmp_ule_cmov(double %a, double %b, i64 %c, i64 %d) {
 ; NOAVX-LABEL: select_fcmp_ule_cmov:
 ; NOAVX:       ## %bb.0:
-; NOAVX-NEXT:    ucomisd %xmm1, %xmm0
-; NOAVX-NEXT:    cmovaq %rsi, %rdi
 ; NOAVX-NEXT:    movq %rdi, %rax
+; NOAVX-NEXT:    ucomisd %xmm1, %xmm0
+; NOAVX-NEXT:    cmovaq %rsi, %rax
 ; NOAVX-NEXT:    retq
 ;
 ; FAST_AVX-LABEL: select_fcmp_ule_cmov:
 ; FAST_AVX:       ## %bb.0:
-; FAST_AVX-NEXT:    vucomisd %xmm1, %xmm0
-; FAST_AVX-NEXT:    cmovaq %rsi, %rdi
 ; FAST_AVX-NEXT:    movq %rdi, %rax
+; FAST_AVX-NEXT:    vucomisd %xmm1, %xmm0
+; FAST_AVX-NEXT:    cmovaq %rsi, %rax
 ; FAST_AVX-NEXT:    retq
   %1 = fcmp ule double %a, %b
   %2 = select i1 %1, i64 %c, i64 %d
@@ -280,30 +280,30 @@ define i64 @select_fcmp_ule_cmov(double %a, double %b, i64 %c, i64 %d) {
 define i64 @select_fcmp_une_cmov(double %a, double %b, i64 %c, i64 %d) {
 ; SDAG-LABEL: select_fcmp_une_cmov:
 ; SDAG:       ## %bb.0:
-; SDAG-NEXT:    ucomisd %xmm1, %xmm0
-; SDAG-NEXT:    cmovneq %rdi, %rsi
-; SDAG-NEXT:    cmovpq %rdi, %rsi
 ; SDAG-NEXT:    movq %rsi, %rax
+; SDAG-NEXT:    ucomisd %xmm1, %xmm0
+; SDAG-NEXT:    cmovneq %rdi, %rax
+; SDAG-NEXT:    cmovpq %rdi, %rax
 ; SDAG-NEXT:    retq
 ;
 ; FAST-LABEL: select_fcmp_une_cmov:
 ; FAST:       ## %bb.0:
-; FAST-NEXT:    ucomisd %xmm1, %xmm0
-; FAST-NEXT:    setp %al
-; FAST-NEXT:    setne %cl
-; FAST-NEXT:    orb %al, %cl
-; FAST-NEXT:    cmoveq %rsi, %rdi
 ; FAST-NEXT:    movq %rdi, %rax
+; FAST-NEXT:    ucomisd %xmm1, %xmm0
+; FAST-NEXT:    setp %cl
+; FAST-NEXT:    setne %dl
+; FAST-NEXT:    orb %cl, %dl
+; FAST-NEXT:    cmoveq %rsi, %rax
 ; FAST-NEXT:    retq
 ;
 ; FAST_AVX-LABEL: select_fcmp_une_cmov:
 ; FAST_AVX:       ## %bb.0:
-; FAST_AVX-NEXT:    vucomisd %xmm1, %xmm0
-; FAST_AVX-NEXT:    setp %al
-; FAST_AVX-NEXT:    setne %cl
-; FAST_AVX-NEXT:    orb %al, %cl
-; FAST_AVX-NEXT:    cmoveq %rsi, %rdi
 ; FAST_AVX-NEXT:    movq %rdi, %rax
+; FAST_AVX-NEXT:    vucomisd %xmm1, %xmm0
+; FAST_AVX-NEXT:    setp %cl
+; FAST_AVX-NEXT:    setne %dl
+; FAST_AVX-NEXT:    orb %cl, %dl
+; FAST_AVX-NEXT:    cmoveq %rsi, %rax
 ; FAST_AVX-NEXT:    retq
   %1 = fcmp une double %a, %b
   %2 = select i1 %1, i64 %c, i64 %d
@@ -323,9 +323,9 @@ define i64 @select_fcmp_true_cmov(double %a, double %b, i64 %c, i64 %d) {
 define i64 @select_icmp_eq_cmov(i64 %a, i64 %b, i64 %c, i64 %d) {
 ; CHECK-LABEL: select_icmp_eq_cmov:
 ; CHECK:       ## %bb.0:
-; CHECK-NEXT:    cmpq %rsi, %rdi
-; CHECK-NEXT:    cmovneq %rcx, %rdx
 ; CHECK-NEXT:    movq %rdx, %rax
+; CHECK-NEXT:    cmpq %rsi, %rdi
+; CHECK-NEXT:    cmovneq %rcx, %rax
 ; CHECK-NEXT:    retq
   %1 = icmp eq i64 %a, %b
   %2 = select i1 %1, i64 %c, i64 %d
@@ -335,9 +335,9 @@ define i64 @select_icmp_eq_cmov(i64 %a, i64 %b, i64 %c, i64 %d) {
 define i64 @select_icmp_ne_cmov(i64 %a, i64 %b, i64 %c, i64 %d) {
 ; CHECK-LABEL: select_icmp_ne_cmov:
 ; CHECK:       ## %bb.0:
-; CHECK-NEXT:    cmpq %rsi, %rdi
-; CHECK-NEXT:    cmoveq %rcx, %rdx
 ; CHECK-NEXT:    movq %rdx, %rax
+; CHECK-NEXT:    cmpq %rsi, %rdi
+; CHECK-NEXT:    cmoveq %rcx, %rax
 ; CHECK-NEXT:    retq
   %1 = icmp ne i64 %a, %b
   %2 = select i1 %1, i64 %c, i64 %d
@@ -347,9 +347,9 @@ define i64 @select_icmp_ne_cmov(i64 %a, i64 %b, i64 %c, i64 %d) {
 define i64 @select_icmp_ugt_cmov(i64 %a, i64 %b, i64 %c, i64 %d) {
 ; CHECK-LABEL: select_icmp_ugt_cmov:
 ; CHECK:       ## %bb.0:
-; CHECK-NEXT:    cmpq %rsi, %rdi
-; CHECK-NEXT:    cmovbeq %rcx, %rdx
 ; CHECK-NEXT:    movq %rdx, %rax
+; CHECK-NEXT:    cmpq %rsi, %rdi
+; CHECK-NEXT:    cmovbeq %rcx, %rax
 ; CHECK-NEXT:    retq
   %1 = icmp ugt i64 %a, %b
   %2 = select i1 %1, i64 %c, i64 %d
@@ -360,9 +360,9 @@ define i64 @select_icmp_ugt_cmov(i64 %a, i64 %b, i64 %c, i64 %d) {
 define i64 @select_icmp_uge_cmov(i64 %a, i64 %b, i64 %c, i64 %d) {
 ; CHECK-LABEL: select_icmp_uge_cmov:
 ; CHECK:       ## %bb.0:
-; CHECK-NEXT:    cmpq %rsi, %rdi
-; CHECK-NEXT:    cmovbq %rcx, %rdx
 ; CHECK-NEXT:    movq %rdx, %rax
+; CHECK-NEXT:    cmpq %rsi, %rdi
+; CHECK-NEXT:    cmovbq %rcx, %rax
 ; CHECK-NEXT:    retq
   %1 = icmp uge i64 %a, %b
   %2 = select i1 %1, i64 %c, i64 %d
@@ -372,9 +372,9 @@ define i64 @select_icmp_uge_cmov(i64 %a, i64 %b, i64 %c, i64 %d) {
 define i64 @select_icmp_ult_cmov(i64 %a, i64 %b, i64 %c, i64 %d) {
 ; CHECK-LABEL: select_icmp_ult_cmov:
 ; CHECK:       ## %bb.0:
-; CHECK-NEXT:    cmpq %rsi, %rdi
-; CHECK-NEXT:    cmovaeq %rcx, %rdx
 ; CHECK-NEXT:    movq %rdx, %rax
+; CHECK-NEXT:    cmpq %rsi, %rdi
+; CHECK-NEXT:    cmovaeq %rcx, %rax
 ; CHECK-NEXT:    retq
   %1 = icmp ult i64 %a, %b
   %2 = select i1 %1, i64 %c, i64 %d
@@ -384,9 +384,9 @@ define i64 @select_icmp_ult_cmov(i64 %a, i64 %b, i64 %c, i64 %d) {
 define i64 @select_icmp_ule_cmov(i64 %a, i64 %b, i64 %c, i64 %d) {
 ; CHECK-LABEL: select_icmp_ule_cmov:
 ; CHECK:       ## %bb.0:
-; CHECK-NEXT:    cmpq %rsi, %rdi
-; CHECK-NEXT:    cmovaq %rcx, %rdx
 ; CHECK-NEXT:    movq %rdx, %rax
+; CHECK-NEXT:    cmpq %rsi, %rdi
+; CHECK-NEXT:    cmovaq %rcx, %rax
 ; CHECK-NEXT:    retq
   %1 = icmp ule i64 %a, %b
   %2 = select i1 %1, i64 %c, i64 %d
@@ -396,9 +396,9 @@ define i64 @select_icmp_ule_cmov(i64 %a, i64 %b, i64 %c, i64 %d) {
 define i64 @select_icmp_sgt_cmov(i64 %a, i64 %b, i64 %c, i64 %d) {
 ; CHECK-LABEL: select_icmp_sgt_cmov:
 ; CHECK:       ## %bb.0:
-; CHECK-NEXT:    cmpq %rsi, %rdi
-; CHECK-NEXT:    cmovleq %rcx, %rdx
 ; CHECK-NEXT:    movq %rdx, %rax
+; CHECK-NEXT:    cmpq %rsi, %rdi
+; CHECK-NEXT:    cmovleq %rcx, %rax
 ; CHECK-NEXT:    retq
   %1 = icmp sgt i64 %a, %b
   %2 = select i1 %1, i64 %c, i64 %d
@@ -408,9 +408,9 @@ define i64 @select_icmp_sgt_cmov(i64 %a, i64 %b, i64 %c, i64 %d) {
 define i64 @select_icmp_sge_cmov(i64 %a, i64 %b, i64 %c, i64 %d) {
 ; CHECK-LABEL: select_icmp_sge_cmov:
 ; CHECK:       ## %bb.0:
-; CHECK-NEXT:    cmpq %rsi, %rdi
-; CHECK-NEXT:    cmovlq %rcx, %rdx
 ; CHECK-NEXT:    movq %rdx, %rax
+; CHECK-NEXT:    cmpq %rsi, %rdi
+; CHECK-NEXT:    cmovlq %rcx, %rax
 ; CHECK-NEXT:    retq
   %1 = icmp sge i64 %a, %b
   %2 = select i1 %1, i64 %c, i64 %d
@@ -420,9 +420,9 @@ define i64 @select_icmp_sge_cmov(i64 %a, i64 %b, i64 %c, i64 %d) {
 define i64 @select_icmp_slt_cmov(i64 %a, i64 %b, i64 %c, i64 %d) {
 ; CHECK-LABEL: select_icmp_slt_cmov:
 ; CHECK:       ## %bb.0:
-; CHECK-NEXT:    cmpq %rsi, %rdi
-; CHECK-NEXT:    cmovgeq %rcx, %rdx
 ; CHECK-NEXT:    movq %rdx, %rax
+; CHECK-NEXT:    cmpq %rsi, %rdi
+; CHECK-NEXT:    cmovgeq %rcx, %rax
 ; CHECK-NEXT:    retq
   %1 = icmp slt i64 %a, %b
   %2 = select i1 %1, i64 %c, i64 %d
@@ -432,9 +432,9 @@ define i64 @select_icmp_slt_cmov(i64 %a, i64 %b, i64 %c, i64 %d) {
 define i64 @select_icmp_sle_cmov(i64 %a, i64 %b, i64 %c, i64 %d) {
 ; CHECK-LABEL: select_icmp_sle_cmov:
 ; CHECK:       ## %bb.0:
-; CHECK-NEXT:    cmpq %rsi, %rdi
-; CHECK-NEXT:    cmovgq %rcx, %rdx
 ; CHECK-NEXT:    movq %rdx, %rax
+; CHECK-NEXT:    cmpq %rsi, %rdi
+; CHECK-NEXT:    cmovgq %rcx, %rax
 ; CHECK-NEXT:    retq
   %1 = icmp sle i64 %a, %b
   %2 = select i1 %1, i64 %c, i64 %d