Add a test case for r176066.

llvm-svn: 176119

1 files changed, 10 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/X86/fast-isel-args-fail.ll b/llvm/test/CodeGen/X86/fast-isel-args-fail.ll
new file mode 100644
index 00000000000..4995baa3e5a
--- /dev/null
+++ b/llvm/test/CodeGen/X86/fast-isel-args-fail.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -fast-isel -verify-machineinstrs -mtriple=x86_64-apple-darwin10
+; Requires: Asserts
+
+; Previously, this would cause an assert.
+define i31 @t1(i31 %a, i31 %b, i31 %c) {
+entry:
+  %add = add nsw i31 %b, %a
+  %add1 = add nsw i31 %add, %c
+  ret i31 %add1
+}