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| author | Sanjay Patel <spatel@rotateright.com> | 2014-12-10 16:58:54 +0000 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2014-12-10 16:58:54 +0000 |
| commit | e20437f9af1064de3e0c6ee89a36169fb12e6bf7 (patch) | |
| tree | 657544797b8fc44a8c0e8df6e372921c41061651 /llvm/test/CodeGen/X86/extractelement-load.ll | |
| parent | 3701450b06cb6698a4af0b225be7679d31acfc31 (diff) | |
| download | bcm5719-llvm-e20437f9af1064de3e0c6ee89a36169fb12e6bf7.tar.gz bcm5719-llvm-e20437f9af1064de3e0c6ee89a36169fb12e6bf7.zip | |
Match new shuffle codegen for MOVHPD patterns
Add patterns to match SSE (shufpd) and AVX (vpermilpd) shuffle codegen
when storing the high element of a v2f64. The existing patterns were
only checking for an unpckh type of shuffle.
http://llvm.org/bugs/show_bug.cgi?id=21791
Differential Revision: http://reviews.llvm.org/D6586
llvm-svn: 223929
Diffstat (limited to 'llvm/test/CodeGen/X86/extractelement-load.ll')
| -rw-r--r-- | llvm/test/CodeGen/X86/extractelement-load.ll | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/llvm/test/CodeGen/X86/extractelement-load.ll b/llvm/test/CodeGen/X86/extractelement-load.ll index 86475997693..732f698f59f 100644 --- a/llvm/test/CodeGen/X86/extractelement-load.ll +++ b/llvm/test/CodeGen/X86/extractelement-load.ll @@ -1,5 +1,6 @@ ; RUN: llc < %s -march=x86 -mattr=+sse2 -mcpu=yonah | FileCheck %s ; RUN: llc < %s -march=x86-64 -mattr=+sse2 -mcpu=core2 | FileCheck %s +; RUN: llc < %s -march=x86-64 -mattr=+avx -mcpu=btver2 | FileCheck %s target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" @@ -29,16 +30,15 @@ undef, i32 7, i32 9, i32 undef, i32 13, i32 15, i32 1, i32 3> ; This case could easily end up inf-looping in the DAG combiner due to an ; low alignment load of the vector which prevents us from reliably forming a ; narrow load. -; FIXME: It would be nice to detect whether the target has fast and legal -; unaligned loads and use them here. + +; The expected codegen is identical for the AVX case except +; load/store instructions will have a leading 'v', so we don't +; need to special-case the checks. + define void @t3() { ; CHECK-LABEL: t3: -; -; This movs the entire vector, shuffling the high double down. If we fixed the -; FIXME above it would just move the high double directly. ; CHECK: movupd -; CHECK: shufpd -; CHECK: movlpd +; CHECK: movhpd bb: %tmp13 = load <2 x double>* undef, align 1 |
