diff options
| author | Craig Topper <craig.topper@intel.com> | 2019-08-08 18:11:17 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2019-08-08 18:11:17 +0000 |
| commit | 9d55e2c85e6636898f58487aea8832d858e7e682 (patch) | |
| tree | 6b413fbc4458c003160997cdf6cf1734bbf4a728 /llvm/test/CodeGen/X86/cmpxchg8b.ll | |
| parent | cb30590da10ba80a133222588efedab7e5fc9bdd (diff) | |
| download | bcm5719-llvm-9d55e2c85e6636898f58487aea8832d858e7e682.tar.gz bcm5719-llvm-9d55e2c85e6636898f58487aea8832d858e7e682.zip | |
[X86] Make CMPXCHG16B feature imply CMPXCHG8B feature.
This fixes znver1 so that it properly enables CMPXHG8B. We can
probably remove explicit CMPXCHG8B from CPUs that also have
CMPXCHG16B, but keeping this simple to allow cherry pick to 9.0.
Fixes PR42935.
llvm-svn: 368324
Diffstat (limited to 'llvm/test/CodeGen/X86/cmpxchg8b.ll')
| -rw-r--r-- | llvm/test/CodeGen/X86/cmpxchg8b.ll | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/cmpxchg8b.ll b/llvm/test/CodeGen/X86/cmpxchg8b.ll index 8eb3dda6b6e..caf40c541e2 100644 --- a/llvm/test/CodeGen/X86/cmpxchg8b.ll +++ b/llvm/test/CodeGen/X86/cmpxchg8b.ll @@ -2,6 +2,7 @@ ; RUN: llc < %s -mtriple=i686-unknown- -mcpu=core2 | FileCheck %s --check-prefixes=CHECK,X86 ; RUN: llc < %s -mtriple=x86_64-unknown- -mcpu=core2 | FileCheck %s --check-prefixes=CHECK,X64 ; RUN: llc < %s -mtriple=i686-unknown- -mcpu=i486 | FileCheck %s --check-prefixes=I486 +; RUN: llc < %s -mtriple=i686-unknown- -mcpu=znver1 | FileCheck %s --check-prefixes=CHECK,X86 ; Basic 64-bit cmpxchg define void @t1(i64* nocapture %p) nounwind ssp { |
