Manually upgrade the test suite to specify the flag to cttz and ctlz.

I followed three heuristics for deciding whether to set 'true' or
'false':

- Everything target independent got 'true' as that is the expected
  common output of the GCC builtins.
- If the target arch only has one way of implementing this operation,
  set the flag in the way that exercises the most of codegen. For most
  architectures this is also the likely path from a GCC builtin, with
  'true' being set. It will (eventually) require lowering away that
  difference, and then lowering to the architecture's operation.
- Otherwise, set the flag differently dependending on which target
  operation should be tested.

Let me know if anyone has any issue with this pattern or would like
specific tests of another form. This should allow the x86 codegen to
just iteratively improve as I teach the backend how to differentiate
between the two forms, and everything else should remain exactly the
same.

llvm-svn: 146370

1 files changed, 7 insertions, 7 deletions

diff --git a/llvm/test/CodeGen/X86/clz.ll b/llvm/test/CodeGen/X86/clz.ll
index d76fab4123b..9b26efd10de 100644
--- a/llvm/test/CodeGen/X86/clz.ll
+++ b/llvm/test/CodeGen/X86/clz.ll
@@ -1,36 +1,36 @@
 ; RUN: llc < %s -march=x86 -mcpu=yonah | FileCheck %s
 
 define i32 @t1(i32 %x) nounwind  {
-	%tmp = tail call i32 @llvm.ctlz.i32( i32 %x )
+	%tmp = tail call i32 @llvm.ctlz.i32( i32 %x, i1 true )
 	ret i32 %tmp
 ; CHECK: t1:
 ; CHECK: bsrl
 ; CHECK: cmov
 }
 
-declare i32 @llvm.ctlz.i32(i32) nounwind readnone 
+declare i32 @llvm.ctlz.i32(i32, i1) nounwind readnone 
 
 define i32 @t2(i32 %x) nounwind  {
-	%tmp = tail call i32 @llvm.cttz.i32( i32 %x )
+	%tmp = tail call i32 @llvm.cttz.i32( i32 %x, i1 true )
 	ret i32 %tmp
 ; CHECK: t2:
 ; CHECK: bsfl
 ; CHECK: cmov
 }
 
-declare i32 @llvm.cttz.i32(i32) nounwind readnone 
+declare i32 @llvm.cttz.i32(i32, i1) nounwind readnone 
 
 define i16 @t3(i16 %x, i16 %y) nounwind  {
 entry:
         %tmp1 = add i16 %x, %y
-	%tmp2 = tail call i16 @llvm.ctlz.i16( i16 %tmp1 )		; <i16> [#uses=1]
+	%tmp2 = tail call i16 @llvm.ctlz.i16( i16 %tmp1, i1 true )		; <i16> [#uses=1]
 	ret i16 %tmp2
 ; CHECK: t3:
 ; CHECK: bsrw
 ; CHECK: cmov
 }
 
-declare i16 @llvm.ctlz.i16(i16) nounwind readnone 
+declare i16 @llvm.ctlz.i16(i16, i1) nounwind readnone 
 
 ; Don't generate the cmovne when the source is known non-zero (and bsr would
 ; not set ZF).
@@ -43,6 +43,6 @@ entry:
 ; CHECK-NOT: cmov
 ; CHECK: ret
   %or = or i32 %n, 1
-  %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %or)
+  %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %or, i1 true)
   ret i32 %tmp1
 }