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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-09-19 18:59:08 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-09-19 18:59:08 +0000 |
| commit | 2d0f20cc043458c945e4959c5b130c07a7f5b8b5 (patch) | |
| tree | 4c6c2685582012433738444bea2cce36c82c7b04 /llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll | |
| parent | 894c39f770298e8972d3518c9b3531b59c819f56 (diff) | |
| download | bcm5719-llvm-2d0f20cc043458c945e4959c5b130c07a7f5b8b5.tar.gz bcm5719-llvm-2d0f20cc043458c945e4959c5b130c07a7f5b8b5.zip | |
[X86] Handle COPYs of physregs better (regalloc hints)
Enable enableMultipleCopyHints() on X86.
Original Patch by @jonpa:
While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling.
Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates.
Differential Revision: https://reviews.llvm.org/D38128
llvm-svn: 342578
Diffstat (limited to 'llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll')
| -rw-r--r-- | llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll b/llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll index c1b11406ae1..1acc83485ce 100644 --- a/llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll +++ b/llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll @@ -193,8 +193,8 @@ define <16 x i1> @bitcast_i16_16i1(i16 zeroext %a0) { define <32 x i1> @bitcast_i32_32i1(i32 %a0) { ; SSE2-SSSE3-LABEL: bitcast_i32_32i1: ; SSE2-SSSE3: # %bb.0: -; SSE2-SSSE3-NEXT: movl %esi, (%rdi) ; SSE2-SSSE3-NEXT: movq %rdi, %rax +; SSE2-SSSE3-NEXT: movl %esi, (%rdi) ; SSE2-SSSE3-NEXT: retq ; ; AVX1-LABEL: bitcast_i32_32i1: @@ -250,14 +250,14 @@ define <32 x i1> @bitcast_i32_32i1(i32 %a0) { define <64 x i1> @bitcast_i64_64i1(i64 %a0) { ; SSE2-SSSE3-LABEL: bitcast_i64_64i1: ; SSE2-SSSE3: # %bb.0: -; SSE2-SSSE3-NEXT: movq %rsi, (%rdi) ; SSE2-SSSE3-NEXT: movq %rdi, %rax +; SSE2-SSSE3-NEXT: movq %rsi, (%rdi) ; SSE2-SSSE3-NEXT: retq ; ; AVX12-LABEL: bitcast_i64_64i1: ; AVX12: # %bb.0: -; AVX12-NEXT: movq %rsi, (%rdi) ; AVX12-NEXT: movq %rdi, %rax +; AVX12-NEXT: movq %rsi, (%rdi) ; AVX12-NEXT: retq ; ; AVX512-LABEL: bitcast_i64_64i1: |
