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| author | Craig Topper <craig.topper@intel.com> | 2018-06-26 01:37:02 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-06-26 01:37:02 +0000 |
| commit | 689e363ff2294f43d2ee35d08777f7a7ea0ce7dd (patch) | |
| tree | 9fbdd280f09e5a2adf4917f2477a50bf8224000a /llvm/test/CodeGen/X86/avx512dq-intrinsics.ll | |
| parent | 9766fd64fba0c3a8a118aee795133a3bab69a0f5 (diff) | |
| download | bcm5719-llvm-689e363ff2294f43d2ee35d08777f7a7ea0ce7dd.tar.gz bcm5719-llvm-689e363ff2294f43d2ee35d08777f7a7ea0ce7dd.zip | |
[X86] Redefine avx512 packed fpclass intrinsics to return a vXi1 mask and implement the mask input argument using an 'and' IR instruction.
This recommits r335562 and 335563 as a single commit.
The frontend will surround the intrinsic with the appropriate marshalling to/from a scalar type to match the sigature of the builtin that software expects.
By exposing the vXi1 type directly in the llvm intrinsic we make it available to optimizers much earlier. This can enable the scalar marshalling code to be optimized away.
llvm-svn: 335568
Diffstat (limited to 'llvm/test/CodeGen/X86/avx512dq-intrinsics.ll')
| -rw-r--r-- | llvm/test/CodeGen/X86/avx512dq-intrinsics.ll | 20 |
1 files changed, 12 insertions, 8 deletions
diff --git a/llvm/test/CodeGen/X86/avx512dq-intrinsics.ll b/llvm/test/CodeGen/X86/avx512dq-intrinsics.ll index e2d25adf3c8..41e0952d51a 100644 --- a/llvm/test/CodeGen/X86/avx512dq-intrinsics.ll +++ b/llvm/test/CodeGen/X86/avx512dq-intrinsics.ll @@ -600,7 +600,7 @@ define <2 x double>@test_int_x86_avx512_mask_range_sd(<2 x double> %x0, <2 x dou ret <2 x double> %res4 } -declare i8 @llvm.x86.avx512.mask.fpclass.pd.512(<8 x double>, i32, i8) +declare <8 x i1> @llvm.x86.avx512.mask.fpclass.pd.512(<8 x double>, i32) define i8 @test_int_x86_avx512_mask_fpclass_pd_512(<8 x double> %x0) { ; CHECK-LABEL: test_int_x86_avx512_mask_fpclass_pd_512: @@ -611,11 +611,13 @@ define i8 @test_int_x86_avx512_mask_fpclass_pd_512(<8 x double> %x0) { ; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77] ; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3] - %res = call i8 @llvm.x86.avx512.mask.fpclass.pd.512(<8 x double> %x0, i32 4, i8 -1) - %res1 = call i8 @llvm.x86.avx512.mask.fpclass.pd.512(<8 x double> %x0, i32 2, i8 %res) - ret i8 %res1 + %res = call <8 x i1> @llvm.x86.avx512.mask.fpclass.pd.512(<8 x double> %x0, i32 4) + %res1 = call <8 x i1> @llvm.x86.avx512.mask.fpclass.pd.512(<8 x double> %x0, i32 2) + %1 = and <8 x i1> %res1, %res + %2 = bitcast <8 x i1> %1 to i8 + ret i8 %2 } -declare i16 @llvm.x86.avx512.mask.fpclass.ps.512(<16 x float>, i32, i16) +declare <16 x i1> @llvm.x86.avx512.mask.fpclass.ps.512(<16 x float>, i32) define i16@test_int_x86_avx512_mask_fpclass_ps_512(<16 x float> %x0) { ; CHECK-LABEL: test_int_x86_avx512_mask_fpclass_ps_512: @@ -626,9 +628,11 @@ define i16@test_int_x86_avx512_mask_fpclass_ps_512(<16 x float> %x0) { ; CHECK-NEXT: # kill: def $ax killed $ax killed $eax ; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77] ; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3] - %res = call i16 @llvm.x86.avx512.mask.fpclass.ps.512(<16 x float> %x0, i32 4, i16 -1) - %res1 = call i16 @llvm.x86.avx512.mask.fpclass.ps.512(<16 x float> %x0, i32 2, i16 %res) - ret i16 %res1 + %res = call <16 x i1> @llvm.x86.avx512.mask.fpclass.ps.512(<16 x float> %x0, i32 4) + %res1 = call <16 x i1> @llvm.x86.avx512.mask.fpclass.ps.512(<16 x float> %x0, i32 2) + %1 = and <16 x i1> %res1, %res + %2 = bitcast <16 x i1> %1 to i16 + ret i16 %2 } declare i8 @llvm.x86.avx512.mask.fpclass.sd(<2 x double>, i32, i8) |
