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| author | Craig Topper <craig.topper@intel.com> | 2017-08-30 16:38:33 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-08-30 16:38:33 +0000 |
| commit | afce0baacd6a10e891518d3f584600de366a5e0b (patch) | |
| tree | 6f795088f69bd2f3fcfc8edded12ff031c274515 /llvm/test/CodeGen/X86/avx512-logic.ll | |
| parent | 89e8d5e9557d29148c9ff118b0e5eb9e6a3a5277 (diff) | |
| download | bcm5719-llvm-afce0baacd6a10e891518d3f584600de366a5e0b.tar.gz bcm5719-llvm-afce0baacd6a10e891518d3f584600de366a5e0b.zip | |
[AVX512] Don't use 32-bit elements version of AND/OR/XOR/ANDN during isel unless we're matching a masked op or broadcast
Selecting 32-bit element logical ops without a select or broadcast requires matching a bitconvert on the inputs to the and. But that's a weird thing to rely on. It's entirely possible that one of the inputs doesn't have a bitcast and one does.
Since there's no functional difference, just remove the extra patterns and save some isel table size.
Differential Revision: https://reviews.llvm.org/D36854
llvm-svn: 312138
Diffstat (limited to 'llvm/test/CodeGen/X86/avx512-logic.ll')
| -rw-r--r-- | llvm/test/CodeGen/X86/avx512-logic.ll | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/llvm/test/CodeGen/X86/avx512-logic.ll b/llvm/test/CodeGen/X86/avx512-logic.ll index 6e08753dbbb..c96c63dd0a4 100644 --- a/llvm/test/CodeGen/X86/avx512-logic.ll +++ b/llvm/test/CodeGen/X86/avx512-logic.ll @@ -7,7 +7,7 @@ define <16 x i32> @vpandd(<16 x i32> %a, <16 x i32> %b) nounwind uwtable readnon ; ALL-LABEL: vpandd: ; ALL: ## BB#0: ## %entry ; ALL-NEXT: vpaddd {{.*}}(%rip){1to16}, %zmm0, %zmm0 -; ALL-NEXT: vpandd %zmm1, %zmm0, %zmm0 +; ALL-NEXT: vpandq %zmm1, %zmm0, %zmm0 ; ALL-NEXT: retq entry: ; Force the execution domain with an add. @@ -21,7 +21,7 @@ define <16 x i32> @vpandnd(<16 x i32> %a, <16 x i32> %b) nounwind uwtable readno ; ALL-LABEL: vpandnd: ; ALL: ## BB#0: ## %entry ; ALL-NEXT: vpaddd {{.*}}(%rip){1to16}, %zmm0, %zmm0 -; ALL-NEXT: vpandnd %zmm0, %zmm1, %zmm0 +; ALL-NEXT: vpandnq %zmm0, %zmm1, %zmm0 ; ALL-NEXT: retq entry: ; Force the execution domain with an add. @@ -37,7 +37,7 @@ define <16 x i32> @vpord(<16 x i32> %a, <16 x i32> %b) nounwind uwtable readnone ; ALL-LABEL: vpord: ; ALL: ## BB#0: ## %entry ; ALL-NEXT: vpaddd {{.*}}(%rip){1to16}, %zmm0, %zmm0 -; ALL-NEXT: vpord %zmm1, %zmm0, %zmm0 +; ALL-NEXT: vporq %zmm1, %zmm0, %zmm0 ; ALL-NEXT: retq entry: ; Force the execution domain with an add. @@ -51,7 +51,7 @@ define <16 x i32> @vpxord(<16 x i32> %a, <16 x i32> %b) nounwind uwtable readnon ; ALL-LABEL: vpxord: ; ALL: ## BB#0: ## %entry ; ALL-NEXT: vpaddd {{.*}}(%rip){1to16}, %zmm0, %zmm0 -; ALL-NEXT: vpxord %zmm1, %zmm0, %zmm0 +; ALL-NEXT: vpxorq %zmm1, %zmm0, %zmm0 ; ALL-NEXT: retq entry: ; Force the execution domain with an add. @@ -132,7 +132,7 @@ define <8 x i64> @orq_broadcast(<8 x i64> %a) nounwind { define <16 x i32> @andd512fold(<16 x i32> %y, <16 x i32>* %x) { ; KNL-LABEL: andd512fold: ; KNL: ## BB#0: ## %entry -; KNL-NEXT: vpandd (%rdi), %zmm0, %zmm0 +; KNL-NEXT: vpandq (%rdi), %zmm0, %zmm0 ; KNL-NEXT: retq ; ; SKX-LABEL: andd512fold: |
