diff options
| author | Craig Topper <craig.topper@intel.com> | 2018-03-20 23:39:48 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-03-20 23:39:48 +0000 |
| commit | d25f1acf6713752b7ec47309b3f7733ba61fa330 (patch) | |
| tree | b50d20cec6e85853ccdf6ff6f8677d0469a28ac2 /llvm/test/CodeGen/X86/avx2-schedule.ll | |
| parent | bb059deacb8d538cf3ff14edc37e892c4301f558 (diff) | |
| download | bcm5719-llvm-d25f1acf6713752b7ec47309b3f7733ba61fa330.tar.gz bcm5719-llvm-d25f1acf6713752b7ec47309b3f7733ba61fa330.zip | |
[X86] Change PMULLD to 10 cycles on Skylake per Agner's tables and llvm-exegesis.
Also restrict to port 0 and 1 for SkylakeClient. It looks like the scheduler models don't account for client not having a full vector ALU on port 5 like server.
Fixes PR36808.
llvm-svn: 328061
Diffstat (limited to 'llvm/test/CodeGen/X86/avx2-schedule.ll')
| -rw-r--r-- | llvm/test/CodeGen/X86/avx2-schedule.ll | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/X86/avx2-schedule.ll b/llvm/test/CodeGen/X86/avx2-schedule.ll index 92c7dfd289c..ca69f05d308 100644 --- a/llvm/test/CodeGen/X86/avx2-schedule.ll +++ b/llvm/test/CodeGen/X86/avx2-schedule.ll @@ -4924,14 +4924,14 @@ define <8 x i32> @test_pmulld(<8 x i32> %a0, <8 x i32> %a1, <8 x i32> *%a2) { ; ; SKYLAKE-LABEL: test_pmulld: ; SKYLAKE: # %bb.0: -; SKYLAKE-NEXT: vpmulld %ymm1, %ymm0, %ymm0 # sched: [8:0.67] -; SKYLAKE-NEXT: vpmulld (%rdi), %ymm0, %ymm0 # sched: [15:0.67] +; SKYLAKE-NEXT: vpmulld %ymm1, %ymm0, %ymm0 # sched: [10:1.00] +; SKYLAKE-NEXT: vpmulld (%rdi), %ymm0, %ymm0 # sched: [17:1.00] ; SKYLAKE-NEXT: retq # sched: [7:1.00] ; ; SKX-LABEL: test_pmulld: ; SKX: # %bb.0: -; SKX-NEXT: vpmulld %ymm1, %ymm0, %ymm0 # sched: [8:0.67] -; SKX-NEXT: vpmulld (%rdi), %ymm0, %ymm0 # sched: [15:0.67] +; SKX-NEXT: vpmulld %ymm1, %ymm0, %ymm0 # sched: [10:0.67] +; SKX-NEXT: vpmulld (%rdi), %ymm0, %ymm0 # sched: [17:0.67] ; SKX-NEXT: retq # sched: [7:1.00] ; ; ZNVER1-LABEL: test_pmulld: |
