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authorBruno Cardoso Lopes <bruno.cardoso@gmail.com>2011-09-08 21:05:43 +0000
committerBruno Cardoso Lopes <bruno.cardoso@gmail.com>2011-09-08 21:05:43 +0000
commit51920a619106673fb1faaa407070f33ff565c5c2 (patch)
tree66eafac19658a3bcb2d4a757e8407a66d29fa845 /llvm/test/CodeGen/X86/avx-blend.ll
parente776b580c1851e800d4fd9f57dc5e634954362aa (diff)
downloadbcm5719-llvm-51920a619106673fb1faaa407070f33ff565c5c2.tar.gz
bcm5719-llvm-51920a619106673fb1faaa407070f33ff565c5c2.zip
Reapply testcase from r139309!
llvm-svn: 139318
Diffstat (limited to 'llvm/test/CodeGen/X86/avx-blend.ll')
-rw-r--r--llvm/test/CodeGen/X86/avx-blend.ll47
1 files changed, 47 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/X86/avx-blend.ll b/llvm/test/CodeGen/X86/avx-blend.ll
new file mode 100644
index 00000000000..dc0d013698b
--- /dev/null
+++ b/llvm/test/CodeGen/X86/avx-blend.ll
@@ -0,0 +1,47 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -promote-elements -mattr=+avx | FileCheck %s
+
+;CHECK: vsel_float
+;CHECK: vblendvps
+;CHECK: ret
+define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
+ %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %v1, <4 x float> %v2
+ ret <4 x float> %vsel
+}
+
+
+;CHECK: vsel_i32
+;CHECK: vblendvps
+;CHECK: ret
+define <4 x i32> @vsel_i32(<4 x i32> %v1, <4 x i32> %v2) {
+ %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i32> %v1, <4 x i32> %v2
+ ret <4 x i32> %vsel
+}
+
+
+;CHECK: vsel_double
+;CHECK: vblendvpd
+;CHECK: ret
+define <2 x double> @vsel_double(<2 x double> %v1, <2 x double> %v2) {
+ %vsel = select <2 x i1> <i1 true, i1 false>, <2 x double> %v1, <2 x double> %v2
+ ret <2 x double> %vsel
+}
+
+
+;CHECK: vsel_i64
+;CHECK: vblendvpd
+;CHECK: ret
+define <2 x i64> @vsel_i64(<2 x i64> %v1, <2 x i64> %v2) {
+ %vsel = select <2 x i1> <i1 true, i1 false>, <2 x i64> %v1, <2 x i64> %v2
+ ret <2 x i64> %vsel
+}
+
+
+;CHECK: vsel_i8
+;CHECK: vpblendvb
+;CHECK: ret
+define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) {
+ %vsel = select <16 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <16 x i8> %v1, <16 x i8> %v2
+ ret <16 x i8> %vsel
+}
+
+
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