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authorTim Northover <tnorthover@apple.com>2014-03-11 10:48:52 +0000
committerTim Northover <tnorthover@apple.com>2014-03-11 10:48:52 +0000
commite94a518a22db4b21f4a4a9e34173a11e9dfc5fcc (patch)
tree054bf7c2cdd888931fdabadb91d82dbb78b05f2b /llvm/test/CodeGen/X86/atomic8.ll
parentaab3cfe023752c32da984afb281d322d631ad298 (diff)
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IR: add a second ordering operand to cmpxhg for failure
The syntax for "cmpxchg" should now look something like: cmpxchg i32* %addr, i32 42, i32 3 acquire monotonic where the second ordering argument gives the required semantics in the case that no exchange takes place. It should be no stronger than the first ordering constraint and cannot be either "release" or "acq_rel" (since no store will have taken place). rdar://problem/15996804 llvm-svn: 203559
Diffstat (limited to 'llvm/test/CodeGen/X86/atomic8.ll')
-rw-r--r--llvm/test/CodeGen/X86/atomic8.ll2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/X86/atomic8.ll b/llvm/test/CodeGen/X86/atomic8.ll
index 3278ed1f504..203b26f0ab9 100644
--- a/llvm/test/CodeGen/X86/atomic8.ll
+++ b/llvm/test/CodeGen/X86/atomic8.ll
@@ -217,7 +217,7 @@ define void @atomic_fetch_umin8(i8 %x) nounwind {
}
define void @atomic_fetch_cmpxchg8() nounwind {
- %t1 = cmpxchg i8* @sc8, i8 0, i8 1 acquire
+ %t1 = cmpxchg i8* @sc8, i8 0, i8 1 acquire acquire
; X64: lock
; X64: cmpxchgb
; X32: lock
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