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| author | David Blaikie <dblaikie@gmail.com> | 2015-02-27 21:17:42 +0000 |
|---|---|---|
| committer | David Blaikie <dblaikie@gmail.com> | 2015-02-27 21:17:42 +0000 |
| commit | a79ac14fa68297f9888bc70a10df5ed9b8864e38 (patch) | |
| tree | 8d8217a8928e3ee599bdde405e2e178b3a55b645 /llvm/test/CodeGen/X86/atom-sched.ll | |
| parent | 83687fb9e654c9d0086e7f6b728c26fa0b729e71 (diff) | |
| download | bcm5719-llvm-a79ac14fa68297f9888bc70a10df5ed9b8864e38.tar.gz bcm5719-llvm-a79ac14fa68297f9888bc70a10df5ed9b8864e38.zip | |
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
llvm-svn: 230794
Diffstat (limited to 'llvm/test/CodeGen/X86/atom-sched.ll')
| -rw-r--r-- | llvm/test/CodeGen/X86/atom-sched.ll | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/X86/atom-sched.ll b/llvm/test/CodeGen/X86/atom-sched.ll index fd18472bff8..b81359e2832 100644 --- a/llvm/test/CodeGen/X86/atom-sched.ll +++ b/llvm/test/CodeGen/X86/atom-sched.ll @@ -21,12 +21,12 @@ define void @func() nounwind uwtable { ; CHECK: movl ; CHECK: imull entry: - %0 = load i32* @b, align 4 - %1 = load i32* @c, align 4 + %0 = load i32, i32* @b, align 4 + %1 = load i32, i32* @c, align 4 %mul = mul nsw i32 %0, %1 store i32 %mul, i32* @a, align 4 - %2 = load i32* @e, align 4 - %3 = load i32* @f, align 4 + %2 = load i32, i32* @e, align 4 + %3 = load i32, i32* @f, align 4 %mul1 = mul nsw i32 %2, %3 store i32 %mul1, i32* @d, align 4 ret void |
