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authorAndrew Trick <atrick@apple.com>2013-11-11 22:40:25 +0000
committerAndrew Trick <atrick@apple.com>2013-11-11 22:40:25 +0000
commita28099fdd4617b8851b1c3a3c96a1e02767f0738 (patch)
treeff76f1630819088794db3466e8b59c758ef838c8 /llvm/test/CodeGen/X86/anyregcc.ll
parent5ae6ed88fb55d12478c118871332f137d2504215 (diff)
downloadbcm5719-llvm-a28099fdd4617b8851b1c3a3c96a1e02767f0738.tar.gz
bcm5719-llvm-a28099fdd4617b8851b1c3a3c96a1e02767f0738.zip
Fix the recently added anyregcc convention to handle spilled operands.
Fixes <rdar://15432754> [JS] Assertion: "Folded a def to a non-store!" The primary purpose of anyregcc is to prevent a patchpoint's call arguments and return value from being spilled. They must be available in a register, although the calling convention does not pin the register. It's up to the front end to avoid using this convention for calls with more arguments than allocatable registers. llvm-svn: 194428
Diffstat (limited to 'llvm/test/CodeGen/X86/anyregcc.ll')
-rw-r--r--llvm/test/CodeGen/X86/anyregcc.ll45
1 files changed, 37 insertions, 8 deletions
diff --git a/llvm/test/CodeGen/X86/anyregcc.ll b/llvm/test/CodeGen/X86/anyregcc.ll
index e238e3cf06f..aa1ed434cbe 100644
--- a/llvm/test/CodeGen/X86/anyregcc.ll
+++ b/llvm/test/CodeGen/X86/anyregcc.ll
@@ -8,11 +8,11 @@
; Num Constants
; CHECK-NEXT: .long 0
; Num Callsites
-; CHECK-NEXT: .long 6
+; CHECK-NEXT: .long 7
; test
; CHECK-NEXT: .long 0
-; CHECK-NEXT: .long L{{.*}}-_test
+; CHECK-LABEL: .long L{{.*}}-_test
; CHECK-NEXT: .short 0
; 3 locations
; CHECK-NEXT: .short 3
@@ -39,7 +39,7 @@ entry:
; property access 1 - %obj is an anyreg call argument and should therefore be in a register
; CHECK-NEXT: .long 1
-; CHECK-NEXT: .long L{{.*}}-_property_access1
+; CHECK-LABEL: .long L{{.*}}-_property_access1
; CHECK-NEXT: .short 0
; 2 locations
; CHECK-NEXT: .short 2
@@ -62,7 +62,7 @@ entry:
; property access 2 - %obj is an anyreg call argument and should therefore be in a register
; CHECK-NEXT: .long 2
-; CHECK-NEXT: .long L{{.*}}-_property_access2
+; CHECK-LABEL: .long L{{.*}}-_property_access2
; CHECK-NEXT: .short 0
; 2 locations
; CHECK-NEXT: .short 2
@@ -86,7 +86,7 @@ entry:
; property access 3 - %obj is a frame index
; CHECK-NEXT: .long 3
-; CHECK-NEXT: .long L{{.*}}-_property_access3
+; CHECK-LABEL: .long L{{.*}}-_property_access3
; CHECK-NEXT: .short 0
; 2 locations
; CHECK-NEXT: .short 2
@@ -110,7 +110,7 @@ entry:
; anyreg_test1
; CHECK-NEXT: .long 4
-; CHECK-NEXT: .long L{{.*}}-_anyreg_test1
+; CHECK-LABEL: .long L{{.*}}-_anyreg_test1
; CHECK-NEXT: .short 0
; 14 locations
; CHECK-NEXT: .short 14
@@ -193,7 +193,7 @@ entry:
; anyreg_test2
; CHECK-NEXT: .long 5
-; CHECK-NEXT: .long L{{.*}}-_anyreg_test2
+; CHECK-LABEL: .long L{{.*}}-_anyreg_test2
; CHECK-NEXT: .short 0
; 14 locations
; CHECK-NEXT: .short 14
@@ -274,6 +274,35 @@ entry:
ret i64 %ret
}
+; Test spilling the return value of an anyregcc call.
+;
+; <rdar://problem/15432754> [JS] Assertion: "Folded a def to a non-store!"
+;
+; CHECK-LABEL: .long 12
+; CHECK-LABEL: .long L{{.*}}-_patchpoint_spilldef
+; CHECK-NEXT: .short 0
+; CHECK-NEXT: .short 3
+; Loc 0: Register (some register that will be spilled to the stack)
+; CHECK-NEXT: .byte 1
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short {{[0-9]+}}
+; CHECK-NEXT: .long 0
+; Loc 1: Register RDI
+; CHECK-NEXT: .byte 1
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 5
+; CHECK-NEXT: .long 0
+; Loc 1: Register RSI
+; CHECK-NEXT: .byte 1
+; CHECK-NEXT: .byte 0
+; CHECK-NEXT: .short 4
+; CHECK-NEXT: .long 0
+define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
+entry:
+ %result = tail call anyregcc i64 (i32, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i32 12, i32 15, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2)
+ tail call void asm sideeffect "nop", "~{ax},~{bx},~{cx},~{dx},~{bp},~{si},~{di},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"() nounwind
+ ret i64 %result
+}
+
declare void @llvm.experimental.patchpoint.void(i32, i32, i8*, i32, ...)
declare i64 @llvm.experimental.patchpoint.i64(i32, i32, i8*, i32, ...)
-
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