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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2015-08-19 21:11:58 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2015-08-19 21:11:58 +0000 |
| commit | 35f528262f47d283023ed0c6a2d12d1da4bc2df3 (patch) | |
| tree | ae542cd0165cba1feb60869819b23f31a598a637 /llvm/test/CodeGen/X86/2011-12-06-AVXVectorExtractCombine.ll | |
| parent | 46db9e822c8aa8ac455d0103901397eb7ff06a4f (diff) | |
| download | bcm5719-llvm-35f528262f47d283023ed0c6a2d12d1da4bc2df3.tar.gz bcm5719-llvm-35f528262f47d283023ed0c6a2d12d1da4bc2df3.zip | |
[DAGCombiner] Added SMAX/SMIN/UMAX/UMIN constant folding
We still need to add constant folding of vector comparisons to fold the tests for targets that don't support the respective min/max nodes
I needed to update 2011-12-06-AVXVectorExtractCombine to load a vector instead of using a constant vector to prevent it folding
Differential Revision: http://reviews.llvm.org/D12118
llvm-svn: 245503
Diffstat (limited to 'llvm/test/CodeGen/X86/2011-12-06-AVXVectorExtractCombine.ll')
| -rw-r--r-- | llvm/test/CodeGen/X86/2011-12-06-AVXVectorExtractCombine.ll | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/llvm/test/CodeGen/X86/2011-12-06-AVXVectorExtractCombine.ll b/llvm/test/CodeGen/X86/2011-12-06-AVXVectorExtractCombine.ll index 2a1a5c9fb3e..e6ba7551421 100644 --- a/llvm/test/CodeGen/X86/2011-12-06-AVXVectorExtractCombine.ll +++ b/llvm/test/CodeGen/X86/2011-12-06-AVXVectorExtractCombine.ll @@ -4,13 +4,14 @@ define void @test(<4 x i32>* nocapture %p) nounwind { ; CHECK-LABEL: test: ; CHECK: vpxor %xmm0, %xmm0, %xmm0 - ; CHECK-NEXT: vpmaxsd {{.*}}, %xmm0, %xmm0 - ; CHECK-NEXT: vmovdqu %xmm0, (%rdi) + ; CHECK-NEXT: vpmaxsd (%rdi), %xmm0, %xmm0 + ; CHECK-NEXT: vmovdqu %xmm0, (%rdi) ; CHECK-NEXT: ret - %a = call <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32> <i32 -8, i32 -9, i32 -10, i32 -11>, <4 x i32> zeroinitializer) nounwind - %b = shufflevector <4 x i32> %a, <4 x i32> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2, i32 3> - %c = shufflevector <8 x i32> %b, <8 x i32> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> - store <4 x i32> %c, <4 x i32>* %p, align 1 + %a = load <4 x i32>, <4 x i32>* %p, align 1 + %b = call <4 x i32> @llvm.x86.sse41.pmaxsd(<4 x i32> %a, <4 x i32> zeroinitializer) nounwind + %c = shufflevector <4 x i32> %b, <4 x i32> undef, <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2, i32 3> + %d = shufflevector <8 x i32> %c, <8 x i32> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> + store <4 x i32> %d, <4 x i32>* %p, align 1 ret void } |
