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authorAndrew Trick <atrick@apple.com>2011-06-15 17:16:12 +0000
committerAndrew Trick <atrick@apple.com>2011-06-15 17:16:12 +0000
commit3013b6ae4ac3a6a141483fd5af7b0995ffb8dcec (patch)
tree1bf327d788e68530283c28edea176108273b4e06 /llvm/test/CodeGen/X86/2011-06-14-PreschedRegalias.ll
parent19a1f425a7f122f5c1734e213d8f7c90a13c68bb (diff)
downloadbcm5719-llvm-3013b6ae4ac3a6a141483fd5af7b0995ffb8dcec.tar.gz
bcm5719-llvm-3013b6ae4ac3a6a141483fd5af7b0995ffb8dcec.zip
Added -stress-sched flag in the Asserts build.
Added a test case for handling physreg aliases during pre-RA-sched. llvm-svn: 133063
Diffstat (limited to 'llvm/test/CodeGen/X86/2011-06-14-PreschedRegalias.ll')
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diff --git a/llvm/test/CodeGen/X86/2011-06-14-PreschedRegalias.ll b/llvm/test/CodeGen/X86/2011-06-14-PreschedRegalias.ll
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index 00000000000..690c27f3ed3
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+++ b/llvm/test/CodeGen/X86/2011-06-14-PreschedRegalias.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march=x86-64 -stress-sched | FileCheck %s
+; Test interference between physreg aliases during preRAsched.
+; mul wants an operand in AL, but call clobbers it.
+
+define i8 @f(i8 %v1, i8 %v2) nounwind {
+entry:
+; CHECK: callq
+; CHECK: movb %{{.*}}, %al
+; CHECK: mulb
+; CHECK: mulb
+ %rval = tail call i8 @bar() nounwind
+ %m1 = mul i8 %v1, %v2
+ %m2 = mul i8 %m1, %rval
+ ret i8 %m2
+}
+
+declare i8 @bar()
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