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| author | Andrew Trick <atrick@apple.com> | 2013-10-15 23:33:07 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2013-10-15 23:33:07 +0000 |
| commit | e97d8d6dde16105555aa148dada45f486b62e07f (patch) | |
| tree | 44c17a8b3f2c5d41724ee132a095be0db559b73e /llvm/test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll | |
| parent | a6c38a32a9ddfc12fbfcc249f40d24d812e5af72 (diff) | |
| download | bcm5719-llvm-e97d8d6dde16105555aa148dada45f486b62e07f.tar.gz bcm5719-llvm-e97d8d6dde16105555aa148dada45f486b62e07f.zip | |
Enable MI Sched for x86.
This changes the SelectionDAG scheduling preference to source
order. Soon, the SelectionDAG scheduler can be bypassed saving
a nice chunk of compile time.
Performance differences that result from this change are often a
consequence of register coalescing. The register coalescer is far from
perfect. Bugs can be filed for deficiencies.
On x86 SandyBridge/Haswell, the source order schedule is often
preserved, particularly for small blocks.
Register pressure is generally improved over the SD scheduler's ILP
mode. However, we are still able to handle large blocks that require
latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also
attempts to discover the critical path in single-block loops and
adjust heuristics accordingly.
The MI scheduler relies on the new machine model. This is currently
unimplemented for AVX, so we may not be generating the best code yet.
Unit tests are updated so they don't depend on SD scheduling heuristics.
llvm-svn: 192750
Diffstat (limited to 'llvm/test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll')
| -rw-r--r-- | llvm/test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll b/llvm/test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll index d4a74c9e7e7..060c535dd77 100644 --- a/llvm/test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll +++ b/llvm/test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll @@ -1,9 +1,9 @@ -; RUN: llc -mcpu=generic -mtriple=i386-apple-darwin -tailcallopt < %s | FileCheck %s +; RUN: llc -mcpu=generic -mtriple=i386-apple-darwin -tailcallopt -enable-misched=false < %s | FileCheck %s ; Check that lowered argumens do not overwrite the return address before it is moved. ; Bug 6225 ; ; If a call is a fastcc tail call and tail call optimization is enabled, the -; caller frame is replaced by the callee frame. This can require that arguments are +; caller frame is replaced by the callee frame. This can require that arguments are ; placed on the former return address stack slot. Special care needs to be taken ; taken that the return address is moved / or stored in a register before ; lowering of arguments potentially overwrites the value. @@ -51,5 +51,3 @@ false: tail call fastcc void @l298(i32 %r10, i32 %r9, i32 %r4) noreturn nounwind ret void } - - |
