[WebAssembly] Fix handling of COPY instructions in WebAssemblyRegStackify.

Move RegStackify after coalescing and teach it to use LiveIntervals instead
of depending on SSA form. This avoids a problem where a register in a COPY
instruction is stackified and then subsequently coalesced with a register
that is not stackified.

This also puts it after the scheduler, which allows us to simplify the
EXPR_STACK constraint, as we no longer have instructions being reordered
after stackification and before coloring.

llvm-svn: 256402

2 files changed, 47 insertions, 9 deletions

diff --git a/llvm/test/CodeGen/WebAssembly/cfg-stackify.ll b/llvm/test/CodeGen/WebAssembly/cfg-stackify.ll
index a10fb614909..71f3551347b 100644
--- a/llvm/test/CodeGen/WebAssembly/cfg-stackify.ll
+++ b/llvm/test/CodeGen/WebAssembly/cfg-stackify.ll
@@ -464,7 +464,7 @@ if.end:
 ; CHECK:      block       BB13_8{{$}}
 ; CHECK-NEXT: block       BB13_7{{$}}
 ; CHECK-NEXT: block       BB13_4{{$}}
-; CHECK-NEXT: br_if       $pop{{[0-9]*}}, BB13_4{{$}}
+; CHECK:      br_if       $pop{{[0-9]*}}, BB13_4{{$}}
 ; CHECK-NEXT: block       BB13_3{{$}}
 ; CHECK:      br_if       $pop{{[0-9]*}}, BB13_3{{$}}
 ; CHECK:      br_if       $pop{{[0-9]*}}, BB13_7{{$}}
@@ -483,7 +483,7 @@ if.end:
 ; OPT:      block       BB13_8{{$}}
 ; OPT-NEXT: block       BB13_7{{$}}
 ; OPT-NEXT: block       BB13_4{{$}}
-; OPT-NEXT: br_if       $pop{{[0-9]*}}, BB13_4{{$}}
+; OPT:      br_if       $pop{{[0-9]*}}, BB13_4{{$}}
 ; OPT-NEXT: block       BB13_3{{$}}
 ; OPT:      br_if       $pop{{[0-9]*}}, BB13_3{{$}}
 ; OPT:      br_if       $pop{{[0-9]*}}, BB13_7{{$}}
@@ -642,7 +642,7 @@ second:
 ; CHECK-NEXT:  loop BB16_5{{$}}
 ; CHECK-NOT:   block
 ; CHECK:       block BB16_4{{$}}
-; CHECK-NEXT:  br_if {{[^,]*}}, BB16_4{{$}}
+; CHECK:       br_if {{[^,]*}}, BB16_4{{$}}
 ; CHECK-NOT:   block
 ; CHECK:       br_if {{[^,]*}}, BB16_1{{$}}
 ; CHECK-NOT:   block
@@ -907,7 +907,7 @@ bb6:
 ; CHECK-NEXT:  br_if        {{[^,]*}}, BB20_4{{$}}
 ; CHECK-NOT:   block
 ; CHECK:       block        BB20_3{{$}}
-; CHECK-NEXT:  br_if        {{[^,]*}}, BB20_3{{$}}
+; CHECK:       br_if        {{[^,]*}}, BB20_3{{$}}
 ; CHECK-NOT:   block
 ; CHECK:       br_if        {{[^,]*}}, BB20_6{{$}}
 ; CHECK-NEXT:  BB20_3:
@@ -933,7 +933,7 @@ bb6:
 ; OPT-NEXT:  br_if        $0, BB20_4{{$}}
 ; OPT-NOT:   block
 ; OPT:       block        BB20_3{{$}}
-; OPT-NEXT:  br_if        $0, BB20_3{{$}}
+; OPT:       br_if        $0, BB20_3{{$}}
 ; OPT-NOT:   block
 ; OPT:       br_if        $0, BB20_8{{$}}
 ; OPT-NEXT:  BB20_3:
@@ -991,7 +991,7 @@ bb8:
 ; CHECK:       block       BB21_7{{$}}
 ; CHECK-NEXT:  block       BB21_6{{$}}
 ; CHECK-NEXT:  block       BB21_4{{$}}
-; CHECK-NEXT:  br_if       {{[^,]*}}, BB21_4{{$}}
+; CHECK:       br_if       {{[^,]*}}, BB21_4{{$}}
 ; CHECK-NOT:   block
 ; CHECK:       br_if       {{[^,]*}}, BB21_7{{$}}
 ; CHECK-NOT:   block
@@ -1015,7 +1015,7 @@ bb8:
 ; OPT:       block       BB21_7{{$}}
 ; OPT-NEXT:  block       BB21_6{{$}}
 ; OPT-NEXT:  block       BB21_4{{$}}
-; OPT-NEXT:  br_if       {{[^,]*}}, BB21_4{{$}}
+; OPT:       br_if       {{[^,]*}}, BB21_4{{$}}
 ; OPT-NOT:   block
 ; OPT:       br_if       {{[^,]*}}, BB21_7{{$}}
 ; OPT-NOT:   block
diff --git a/llvm/test/CodeGen/WebAssembly/reg-stackify.ll b/llvm/test/CodeGen/WebAssembly/reg-stackify.ll
index 3c343434836..1c1b1e193f7 100644
--- a/llvm/test/CodeGen/WebAssembly/reg-stackify.ll
+++ b/llvm/test/CodeGen/WebAssembly/reg-stackify.ll
@@ -53,8 +53,9 @@ define i32 @yes1(i32* %q) {
 ; CHECK-NEXT: .param i32, i32, i32, i32{{$}}
 ; CHECK-NEXT: .result i32{{$}}
 ; CHECK-NEXT: .local i32, i32{{$}}
-; CHECK-NEXT: i32.const   $4=, 1{{$}}
 ; CHECK-NEXT: i32.const   $5=, 2{{$}}
+; CHECK-NEXT: i32.const   $4=, 1{{$}}
+; CHECK-NEXT: block       BB4_2{{$}}
 ; CHECK-NEXT: i32.lt_s    $push0=, $0, $4{{$}}
 ; CHECK-NEXT: i32.lt_s    $push1=, $1, $5{{$}}
 ; CHECK-NEXT: i32.xor     $push4=, $pop0, $pop1{{$}}
@@ -63,7 +64,6 @@ define i32 @yes1(i32* %q) {
 ; CHECK-NEXT: i32.xor     $push5=, $pop2, $pop3{{$}}
 ; CHECK-NEXT: i32.xor     $push6=, $pop4, $pop5{{$}}
 ; CHECK-NEXT: i32.ne      $push7=, $pop6, $4{{$}}
-; CHECK-NEXT: block       BB4_2{{$}}
 ; CHECK-NEXT: br_if       $pop7, BB4_2{{$}}
 ; CHECK-NEXT: i32.const   $push8=, 0{{$}}
 ; CHECK-NEXT: return      $pop8{{$}}
@@ -85,4 +85,42 @@ false:
   ret i32 1
 }
 
+; Test an interesting case where the load has multiple uses and cannot
+; be trivially stackified.
+
+; CHECK-LABEL: multiple_uses:
+; CHECK-NEXT: .param      i32, i32, i32{{$}}
+; CHECK-NEXT: .local      i32{{$}}
+; CHECK-NEXT: i32.load    $3=, 0($2){{$}}
+; CHECK-NEXT: block       BB5_3{{$}}
+; CHECK-NEXT: i32.ge_u    $push0=, $3, $1{{$}}
+; CHECK-NEXT: br_if       $pop0, BB5_3{{$}}
+; CHECK-NEXT: i32.lt_u    $push1=, $3, $0{{$}}
+; CHECK-NEXT: br_if       $pop1, BB5_3{{$}}
+; CHECK-NEXT: i32.store   $discard=, 0($2), $3{{$}}
+; CHECK-NEXT: BB5_3:
+; CHECK-NEXT: return{{$}}
+define void @multiple_uses(i32* %arg0, i32* %arg1, i32* %arg2) nounwind {
+bb:
+  br label %loop
+
+loop:
+  %tmp7 = load i32, i32* %arg2
+  %tmp8 = inttoptr i32 %tmp7 to i32*
+  %tmp9 = icmp uge i32* %tmp8, %arg1
+  %tmp10 = icmp ult i32* %tmp8, %arg0
+  %tmp11 = or i1 %tmp9, %tmp10
+  br i1 %tmp11, label %back, label %then
+
+then:
+  store i32 %tmp7, i32* %arg2
+  br label %back
+
+back:
+  br i1 undef, label %return, label %loop
+
+return:
+  ret void
+}
+
 !0 = !{}