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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-04-06 11:00:51 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-04-06 11:00:51 +0000 |
| commit | 8a83f16ccd089224e7e84c0a1524296fccf61419 (patch) | |
| tree | d0808a41e9a7c61b8da4daa668f95106bcd7dec8 /llvm/test/CodeGen/WebAssembly/stack-alignment.ll | |
| parent | da8b71f292976eb64cb5a07d0ba8b5960cc3a973 (diff) | |
| download | bcm5719-llvm-8a83f16ccd089224e7e84c0a1524296fccf61419.tar.gz bcm5719-llvm-8a83f16ccd089224e7e84c0a1524296fccf61419.zip | |
[X86][SandyBridge] SBWriteResPair +5cy Memory Folds
As mentioned on D44647, this patch increases the default memory latency to +5cy , which more closely matches what most custom cases are doing for reg-mem instructions.
I've bumped LoadLatency, ReadAfterLd and WriteLoad values to 5cy to be consistent.
As Sandy Bridge is currently our default generic model, this affects a lot of scheduling tests...
Differential Revision: https://reviews.llvm.org/D44654
llvm-svn: 329388
Diffstat (limited to 'llvm/test/CodeGen/WebAssembly/stack-alignment.ll')
0 files changed, 0 insertions, 0 deletions
