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| author | Thomas Lively <tlively@google.com> | 2019-01-08 06:25:55 +0000 |
|---|---|---|
| committer | Thomas Lively <tlively@google.com> | 2019-01-08 06:25:55 +0000 |
| commit | 6a87ddac9a056c9a7b75eb630908aa356d8a1028 (patch) | |
| tree | 23cc1254457e558cb7c6ea53d8601517fea5c34d /llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll | |
| parent | 616ed1722111a3dcb5d339fe6ce8a5f6d69bdc80 (diff) | |
| download | bcm5719-llvm-6a87ddac9a056c9a7b75eb630908aa356d8a1028.tar.gz bcm5719-llvm-6a87ddac9a056c9a7b75eb630908aa356d8a1028.zip | |
[WebAssembly] Massive instruction renaming
Summary:
An automated renaming of all the instructions listed at
https://github.com/WebAssembly/spec/issues/884#issuecomment-426433329
as well as some similarly-named identifiers.
Reviewers: aheejin, dschuff, aardappel
Subscribers: sbc100, jgravelle-google, eraman, sunfish, jfb, llvm-commits
Differential Revision: https://reviews.llvm.org/D56338
llvm-svn: 350609
Diffstat (limited to 'llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll')
| -rw-r--r-- | llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll b/llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll index 48457a6fa52..de991896c98 100644 --- a/llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll +++ b/llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll @@ -204,7 +204,7 @@ define <4 x i32> @bitselect_v4i32(<4 x i32> %c, <4 x i32> %v1, <4 x i32> %v2) { ; CHECK-LABEL: trunc_sat_s_v4i32: ; NO-SIMD128-NOT: f32x4 ; SIMD128-NEXT: .functype trunc_sat_s_v4i32 (v128) -> (v128){{$}} -; SIMD128-NEXT: i32x4.trunc_sat_s/f32x4 $push[[R:[0-9]+]]=, $0 +; SIMD128-NEXT: i32x4.trunc_sat_f32x4_s $push[[R:[0-9]+]]=, $0 ; SIMD128-NEXT: return $pop[[R]] declare <4 x i32> @llvm.wasm.trunc.saturate.signed.v4i32.v4f32(<4 x float>) define <4 x i32> @trunc_sat_s_v4i32(<4 x float> %x) { @@ -215,7 +215,7 @@ define <4 x i32> @trunc_sat_s_v4i32(<4 x float> %x) { ; CHECK-LABEL: trunc_sat_u_v4i32: ; NO-SIMD128-NOT: f32x4 ; SIMD128-NEXT: .functype trunc_sat_u_v4i32 (v128) -> (v128){{$}} -; SIMD128-NEXT: i32x4.trunc_sat_u/f32x4 $push[[R:[0-9]+]]=, $0 +; SIMD128-NEXT: i32x4.trunc_sat_f32x4_u $push[[R:[0-9]+]]=, $0 ; SIMD128-NEXT: return $pop[[R]] declare <4 x i32> @llvm.wasm.trunc.saturate.unsigned.v4i32.v4f32(<4 x float>) define <4 x i32> @trunc_sat_u_v4i32(<4 x float> %x) { @@ -261,7 +261,7 @@ define <2 x i64> @bitselect_v2i64(<2 x i64> %c, <2 x i64> %v1, <2 x i64> %v2) { ; CHECK-LABEL: trunc_sat_s_v2i64: ; NO-SIMD128-NOT: f32x4 ; SIMD128-NEXT: .functype trunc_sat_s_v2i64 (v128) -> (v128){{$}} -; SIMD128-NEXT: i64x2.trunc_sat_s/f64x2 $push[[R:[0-9]+]]=, $0 +; SIMD128-NEXT: i64x2.trunc_sat_f64x2_s $push[[R:[0-9]+]]=, $0 ; SIMD128-NEXT: return $pop[[R]] declare <2 x i64> @llvm.wasm.trunc.saturate.signed.v2i64.v2f64(<2 x double>) define <2 x i64> @trunc_sat_s_v2i64(<2 x double> %x) { @@ -272,7 +272,7 @@ define <2 x i64> @trunc_sat_s_v2i64(<2 x double> %x) { ; CHECK-LABEL: trunc_sat_u_v2i64: ; NO-SIMD128-NOT: f32x4 ; SIMD128-NEXT: .functype trunc_sat_u_v2i64 (v128) -> (v128){{$}} -; SIMD128-NEXT: i64x2.trunc_sat_u/f64x2 $push[[R:[0-9]+]]=, $0 +; SIMD128-NEXT: i64x2.trunc_sat_f64x2_u $push[[R:[0-9]+]]=, $0 ; SIMD128-NEXT: return $pop[[R]] declare <2 x i64> @llvm.wasm.trunc.saturate.unsigned.v2i64.v2f64(<2 x double>) define <2 x i64> @trunc_sat_u_v2i64(<2 x double> %x) { |
