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| author | Thomas Lively <tlively@google.com> | 2018-10-11 00:01:25 +0000 |
|---|---|---|
| committer | Thomas Lively <tlively@google.com> | 2018-10-11 00:01:25 +0000 |
| commit | 2ebacb107bfebc7b60b238edea538570ad44cef9 (patch) | |
| tree | e2dcbd81ba4e02e85be7096afe91d40b1ea5dce3 /llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll | |
| parent | 7b2b0185ba6c4b21906310183e92e8b32f43a0d7 (diff) | |
| download | bcm5719-llvm-2ebacb107bfebc7b60b238edea538570ad44cef9.tar.gz bcm5719-llvm-2ebacb107bfebc7b60b238edea538570ad44cef9.zip | |
[WebAssembly] Saturating float to int intrinsics
Summary:
Although the saturating float to int instructions are already
emitted from normal IR, the fpto{s,u}i instructions produce poison
values if the argument cannot fit in the result type. These intrinsics
are therefore necessary to get guaranteed defined saturating behavior.
Reviewers: aheejin, dschuff
Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D53004
llvm-svn: 344204
Diffstat (limited to 'llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll')
| -rw-r--r-- | llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll b/llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll index f9f4eb0cf9e..ab32929ceb8 100644 --- a/llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll +++ b/llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll @@ -226,6 +226,30 @@ define <4 x i32> @bitselect_v4i32(<4 x i32> %c, <4 x i32> %v1, <4 x i32> %v2) { ret <4 x i32> %a } +; CHECK-LABEL: trunc_sat_s_v4i32: +; NO-SIMD128-NOT: f32x4 +; SIMD128-NEXT: .param v128{{$}} +; SIMD128-NEXT: .result v128{{$}} +; SIMD128-NEXT: i32x4.trunc_sat_s/f32x4 $push[[R:[0-9]+]]=, $0 +; SIMD128-NEXT: return $pop[[R]] +declare <4 x i32> @llvm.wasm.trunc.saturate.signed.v4i32.v4f32(<4 x float>) +define <4 x i32> @trunc_sat_s_v4i32(<4 x float> %x) { + %a = call <4 x i32> @llvm.wasm.trunc.saturate.signed.v4i32.v4f32(<4 x float> %x) + ret <4 x i32> %a +} + +; CHECK-LABEL: trunc_sat_u_v4i32: +; NO-SIMD128-NOT: f32x4 +; SIMD128-NEXT: .param v128{{$}} +; SIMD128-NEXT: .result v128{{$}} +; SIMD128-NEXT: i32x4.trunc_sat_u/f32x4 $push[[R:[0-9]+]]=, $0 +; SIMD128-NEXT: return $pop[[R]] +declare <4 x i32> @llvm.wasm.trunc.saturate.unsigned.v4i32.v4f32(<4 x float>) +define <4 x i32> @trunc_sat_u_v4i32(<4 x float> %x) { + %a = call <4 x i32> @llvm.wasm.trunc.saturate.unsigned.v4i32.v4f32(<4 x float> %x) + ret <4 x i32> %a +} + ; ============================================================================== ; 2 x i64 ; ============================================================================== @@ -264,6 +288,30 @@ define <2 x i64> @bitselect_v2i64(<2 x i64> %c, <2 x i64> %v1, <2 x i64> %v2) { ret <2 x i64> %a } +; CHECK-LABEL: trunc_sat_s_v2i64: +; NO-SIMD128-NOT: f32x4 +; SIMD128-NEXT: .param v128{{$}} +; SIMD128-NEXT: .result v128{{$}} +; SIMD128-NEXT: i64x2.trunc_sat_s/f64x2 $push[[R:[0-9]+]]=, $0 +; SIMD128-NEXT: return $pop[[R]] +declare <2 x i64> @llvm.wasm.trunc.saturate.signed.v2i64.v2f64(<2 x double>) +define <2 x i64> @trunc_sat_s_v2i64(<2 x double> %x) { + %a = call <2 x i64> @llvm.wasm.trunc.saturate.signed.v2i64.v2f64(<2 x double> %x) + ret <2 x i64> %a +} + +; CHECK-LABEL: trunc_sat_u_v2i64: +; NO-SIMD128-NOT: f32x4 +; SIMD128-NEXT: .param v128{{$}} +; SIMD128-NEXT: .result v128{{$}} +; SIMD128-NEXT: i64x2.trunc_sat_u/f64x2 $push[[R:[0-9]+]]=, $0 +; SIMD128-NEXT: return $pop[[R]] +declare <2 x i64> @llvm.wasm.trunc.saturate.unsigned.v2i64.v2f64(<2 x double>) +define <2 x i64> @trunc_sat_u_v2i64(<2 x double> %x) { + %a = call <2 x i64> @llvm.wasm.trunc.saturate.unsigned.v2i64.v2f64(<2 x double> %x) + ret <2 x i64> %a +} + ; ============================================================================== ; 4 x f32 ; ============================================================================== |
