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author | Thomas Lively <tlively@google.com> | 2019-09-27 02:06:50 +0000 |
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committer | Thomas Lively <tlively@google.com> | 2019-09-27 02:06:50 +0000 |
commit | 81125f7362f63adf6e90b35adf9c4bd809208b95 (patch) | |
tree | 5028f79c5c0986df99d3b16145e378ea3332e416 /llvm/test/CodeGen/WebAssembly/simd-ext-load-trunc-store.ll | |
parent | 695a8bd6a031a4e00d990b59bd1549dd02bfc829 (diff) | |
download | bcm5719-llvm-81125f7362f63adf6e90b35adf9c4bd809208b95.tar.gz bcm5719-llvm-81125f7362f63adf6e90b35adf9c4bd809208b95.zip |
[WebAssembly] SIMD Load and extend operations
Summary:
As specified at
https://github.com/webassembly/simd/blob/master/proposals/simd/SIMD.md#load-and-extend.
These instructions are behind the unimplemented-simd128 target feature
for now because they have not been implemented in V8 yet.
Reviewers: aheejin
Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68058
llvm-svn: 373040
Diffstat (limited to 'llvm/test/CodeGen/WebAssembly/simd-ext-load-trunc-store.ll')
-rw-r--r-- | llvm/test/CodeGen/WebAssembly/simd-ext-load-trunc-store.ll | 57 |
1 files changed, 0 insertions, 57 deletions
diff --git a/llvm/test/CodeGen/WebAssembly/simd-ext-load-trunc-store.ll b/llvm/test/CodeGen/WebAssembly/simd-ext-load-trunc-store.ll deleted file mode 100644 index 39bcc1d0bde..00000000000 --- a/llvm/test/CodeGen/WebAssembly/simd-ext-load-trunc-store.ll +++ /dev/null @@ -1,57 +0,0 @@ -; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+unimplemented-simd128 | FileCheck %s - -; Check that store in memory with smaller lanes are loaded and stored -; as expected. This is a regression test for part of bug 39275. - -target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" -target triple = "wasm32-unknown-unknown" - -; CHECK-LABEL: load_ext_2xi32: -; CHECK-NEXT: .functype load_ext_2xi32 (i32) -> (v128){{$}} -; CHECK-NEXT: i64.load32_u $push[[L0:[0-9]+]]=, 0($0){{$}} -; CHECK-NEXT: i64x2.splat $push[[L1:[0-9]+]]=, $pop[[L0]]{{$}} -; CHECK-NEXT: i64.load32_u $push[[L2:[0-9]+]]=, 4($0){{$}} -; CHECK-NEXT: i64x2.replace_lane $push[[R:[0-9]+]]=, $pop[[L1]], 1, $pop[[L2]]{{$}} -; CHECK-NEXT: return $pop[[R]]{{$}} -define <2 x i32> @load_ext_2xi32(<2 x i32>* %p) { - %1 = load <2 x i32>, <2 x i32>* %p, align 4 - ret <2 x i32> %1 -} - -; CHECK-LABEL: load_zext_2xi32: -; CHECK-NEXT: .functype load_zext_2xi32 (i32) -> (v128){{$}} -; CHECK-NEXT: i64.load32_u $push[[L0:[0-9]+]]=, 0($0){{$}} -; CHECK-NEXT: i64x2.splat $push[[L1:[0-9]+]]=, $pop[[L0]]{{$}} -; CHECK-NEXT: i64.load32_u $push[[L2:[0-9]+]]=, 4($0){{$}} -; CHECK-NEXT: i64x2.replace_lane $push[[R:[0-9]+]]=, $pop[[L1]], 1, $pop[[L2]]{{$}} -; CHECK-NEXT: return $pop[[R]]{{$}} -define <2 x i64> @load_zext_2xi32(<2 x i32>* %p) { - %1 = load <2 x i32>, <2 x i32>* %p, align 4 - %2 = zext <2 x i32> %1 to <2 x i64> - ret <2 x i64> %2 -} - -; CHECK-LABEL: load_sext_2xi32: -; CHECK-NEXT: .functype load_sext_2xi32 (i32) -> (v128){{$}} -; CHECK-NEXT: i64.load32_s $push[[L0:[0-9]+]]=, 0($0){{$}} -; CHECK-NEXT: i64x2.splat $push[[L1:[0-9]+]]=, $pop[[L0]]{{$}} -; CHECK-NEXT: i64.load32_s $push[[L2:[0-9]+]]=, 4($0){{$}} -; CHECK-NEXT: i64x2.replace_lane $push[[R:[0-9]+]]=, $pop[[L1]], 1, $pop[[L2]]{{$}} -; CHECK-NEXT: return $pop[[R]]{{$}} -define <2 x i64> @load_sext_2xi32(<2 x i32>* %p) { - %1 = load <2 x i32>, <2 x i32>* %p, align 4 - %2 = sext <2 x i32> %1 to <2 x i64> - ret <2 x i64> %2 -} - -; CHECK-LABEL: store_trunc_2xi32: -; CHECK-NEXT: .functype store_trunc_2xi32 (i32, v128) -> (){{$}} -; CHECK-NEXT: i64x2.extract_lane $push[[L0:[0-9]+]]=, $1, 1 -; CHECK-NEXT: i64.store32 4($0), $pop[[L0]] -; CHECK-NEXT: i64x2.extract_lane $push[[L1:[0-9]+]]=, $1, 0 -; CHECK-NEXT: i64.store32 0($0), $pop[[L1]] -; CHECK-NEXT: return -define void @store_trunc_2xi32(<2 x i32>* %p, <2 x i32> %x) { - store <2 x i32> %x, <2 x i32>* %p, align 4 - ret void -} |