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authorEli Friedman <efriedma@codeaurora.org>2018-08-14 22:10:25 +0000
committerEli Friedman <efriedma@codeaurora.org>2018-08-14 22:10:25 +0000
commit0d12e90bf5ad2200dca59a21fe543aabba6b7b2e (patch)
treebf5bdb8cbf97bc8aef9ef1fe240f1212870541db /llvm/test/CodeGen/WebAssembly/exception.ll
parent0f22fac2742bd3e382bba577671c19841ac2b5f7 (diff)
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[ARM] Make PerformSHLSimplify add nodes to the DAG worklist correctly.
Intentionally excluding nodes from the DAGCombine worklist is likely to lead to weird optimizations and infinite loops, so it's generally a bad idea. To avoid the infinite loops, fix DAGCombine to use the isDesirableToCommuteWithShift target hook before performing the transforms in question, and implement the target hook in the ARM backend disable the transforms in question. Fixes https://bugs.llvm.org/show_bug.cgi?id=38530 . (I don't have a reduced testcase for that bug. But we should have sufficient test coverage for PerformSHLSimplify given that we're not playing weird tricks with the worklist. I can try to bugpoint it if necessary, though.) Differential Revision: https://reviews.llvm.org/D50667 llvm-svn: 339734
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