[ARM] Materialise some boolean values to avoid a branch

This patch combines some cases of ARMISD::CMOV for integers that arise in comparisons of the form

  a != b ? x : 0
  a == b ? 0 : x

and that currently (e.g. in Thumb1) are emitted as branches.

Differential Revision: https://reviews.llvm.org/D34515

llvm-svn: 325323

3 files changed, 70 insertions, 95 deletions

diff --git a/llvm/test/CodeGen/Thumb/branchless-cmp.ll b/llvm/test/CodeGen/Thumb/branchless-cmp.ll
index 6d700997ada..6c6c905c5d3 100644
--- a/llvm/test/CodeGen/Thumb/branchless-cmp.ll
+++ b/llvm/test/CodeGen/Thumb/branchless-cmp.ll
@@ -1,149 +1,109 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=thumb-eabi -mcpu=cortex-m0 %s -verify-machineinstrs -o - | FileCheck %s
 
 define i32 @test1a(i32 %a, i32 %b) {
-; CHECK-LABEL: test1a:
-; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    mov r2, r0
-; CHECK-NEXT:    movs r0, #1
-; CHECK-NEXT:    movs r3, #0
-; CHECK-NEXT:    cmp r2, r1
-; CHECK-NEXT:    bne .LBB0_2
-; CHECK-NEXT:  @ %bb.1: @ %entry
-; CHECK-NEXT:    mov r0, r3
-; CHECK-NEXT:  .LBB0_2: @ %entry
-; CHECK-NEXT:    bx lr
 entry:
   %cmp = icmp ne i32 %a, %b
   %cond = zext i1 %cmp to i32
   ret i32 %cond
+; CHECK-LABEL: test1a:
+; CHECK-NOT: b{{(ne)|(eq)}}
+; CHECK:       subs r0, r0, r1
+; CHECK-NEXT:  subs r1, r0, #1
+; CHECK-NEXT:  sbcs r0, r1
 }
 
 define i32 @test1b(i32 %a, i32 %b) {
-; CHECK-LABEL: test1b:
-; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    mov r2, r0
-; CHECK-NEXT:    movs r0, #1
-; CHECK-NEXT:    movs r3, #0
-; CHECK-NEXT:    cmp r2, r1
-; CHECK-NEXT:    beq .LBB1_2
-; CHECK-NEXT:  @ %bb.1: @ %entry
-; CHECK-NEXT:    mov r0, r3
-; CHECK-NEXT:  .LBB1_2: @ %entry
-; CHECK-NEXT:    bx lr
 entry:
   %cmp = icmp eq i32 %a, %b
   %cond = zext i1 %cmp to i32
   ret i32 %cond
+; CHECK-LABEL: test1b:
+; CHECK-NOT: b{{(ne)|(eq)}}
+; CHECK:       subs    r1, r0, r1
+; CHECK-NEXT:  movs    r0, #0
+; CHECK-NEXT:  subs    r0, r0, r1
+; CHECK-NEXT:  adcs    r0, r1
 }
 
 define i32 @test2a(i32 %a, i32 %b) {
-; CHECK-LABEL: test2a:
-; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    mov r2, r0
-; CHECK-NEXT:    movs r0, #1
-; CHECK-NEXT:    movs r3, #0
-; CHECK-NEXT:    cmp r2, r1
-; CHECK-NEXT:    beq .LBB2_2
-; CHECK-NEXT:  @ %bb.1: @ %entry
-; CHECK-NEXT:    mov r0, r3
-; CHECK-NEXT:  .LBB2_2: @ %entry
-; CHECK-NEXT:    bx lr
 entry:
   %cmp = icmp eq i32 %a, %b
   %cond = zext i1 %cmp to i32
   ret i32 %cond
+; CHECK-LABEL: test2a:
+; CHECK-NOT: b{{(ne)|(eq)}}
+; CHECK:       subs    r1, r0, r1
+; CHECK-NEXT:  movs    r0, #0
+; CHECK-NEXT:  subs    r0, r0, r1
+; CHECK-NEXT:  adcs    r0, r1
 }
 
 define i32 @test2b(i32 %a, i32 %b) {
-; CHECK-LABEL: test2b:
-; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    mov r2, r0
-; CHECK-NEXT:    movs r0, #1
-; CHECK-NEXT:    movs r3, #0
-; CHECK-NEXT:    cmp r2, r1
-; CHECK-NEXT:    bne .LBB3_2
-; CHECK-NEXT:  @ %bb.1: @ %entry
-; CHECK-NEXT:    mov r0, r3
-; CHECK-NEXT:  .LBB3_2: @ %entry
-; CHECK-NEXT:    bx lr
 entry:
   %cmp = icmp ne i32 %a, %b
   %cond = zext i1 %cmp to i32
   ret i32 %cond
+; CHECK-LABEL: test2b:
+; CHECK-NOT: b{{(ne)|(eq)}}
+; CHECK:       subs    r0, r0, r1
+; CHECK-NEXT:  subs    r1, r0, #1
+; CHECK-NEXT:  sbcs    r0, r1
 }
 
 define i32 @test3a(i32 %a, i32 %b) {
-; CHECK-LABEL: test3a:
-; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    mov r2, r0
-; CHECK-NEXT:    movs r0, #0
-; CHECK-NEXT:    movs r3, #4
-; CHECK-NEXT:    cmp r2, r1
-; CHECK-NEXT:    beq .LBB4_2
-; CHECK-NEXT:  @ %bb.1: @ %entry
-; CHECK-NEXT:    mov r0, r3
-; CHECK-NEXT:  .LBB4_2: @ %entry
-; CHECK-NEXT:    bx lr
 entry:
   %cmp = icmp eq i32 %a, %b
   %cond = select i1 %cmp, i32 0, i32 4
   ret i32 %cond
+; CHECK-LABEL: test3a:
+; CHECK-NOT: b{{(ne)|(eq)}}
+; CHECK:       subs    r0, r0, r1
+; CHECK-NEXT:  subs    r1, r0, #1
+; CHECK-NEXT:  sbcs    r0, r1
+; CHECK-NEXT:  lsls    r0, r0, #2
 }
 
 define i32 @test3b(i32 %a, i32 %b) {
-; CHECK-LABEL: test3b:
-; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    movs r2, #1
-; CHECK-NEXT:    movs r3, #0
-; CHECK-NEXT:    cmp r0, r1
-; CHECK-NEXT:    beq .LBB5_2
-; CHECK-NEXT:  @ %bb.1: @ %entry
-; CHECK-NEXT:    mov r2, r3
-; CHECK-NEXT:  .LBB5_2: @ %entry
-; CHECK-NEXT:    lsls r0, r2, #2
-; CHECK-NEXT:    bx lr
 entry:
   %cmp = icmp eq i32 %a, %b
   %cond = select i1 %cmp, i32 4, i32 0
   ret i32 %cond
+; CHECK-LABEL: test3b:
+; CHECK-NOT: b{{(ne)|(eq)}}
+; CHECK:      subs	r0, r0, r1
+; CHECK-NEXT: movs	r1, #0
+; CHECK-NEXT: subs	r1, r1, r0
+; CHECK-NEXT: adcs	r1, r0
+; CHECK-NEXT: lsls	r0, r1, #2
 }
 
 ; FIXME: This one hasn't changed actually
 ; but could look like test3b
 define i32 @test4a(i32 %a, i32 %b) {
-; CHECK-LABEL: test4a:
-; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    mov r2, r0
-; CHECK-NEXT:    movs r0, #0
-; CHECK-NEXT:    movs r3, #4
-; CHECK-NEXT:    cmp r2, r1
-; CHECK-NEXT:    bne .LBB6_2
-; CHECK-NEXT:  @ %bb.1: @ %entry
-; CHECK-NEXT:    mov r0, r3
-; CHECK-NEXT:  .LBB6_2: @ %entry
-; CHECK-NEXT:    bx lr
 entry:
   %cmp = icmp ne i32 %a, %b
   %cond = select i1 %cmp, i32 0, i32 4
   ret i32 %cond
+; CHECK-LABEL: test4a:
+; CHECK-NOT: b{{(ne)|(eq)}}
+; CHECK:       mov     r2, r0
+; CHECK-NEXT:  movs    r0, #0
+; CHECK-NEXT:  movs    r3, #4
+; CHECK-NEXT:  cmp     r2, r1
+; CHECK-NEXT:  bne     .[[BRANCH:[A-Z0-9_]+]]
+; CHECK:       mov     r0, r3
+; CHECK:       .[[BRANCH]]:
 }
 
 define i32 @test4b(i32 %a, i32 %b) {
-; CHECK-LABEL: test4b:
-; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    movs r2, #1
-; CHECK-NEXT:    movs r3, #0
-; CHECK-NEXT:    cmp r0, r1
-; CHECK-NEXT:    bne .LBB7_2
-; CHECK-NEXT:  @ %bb.1: @ %entry
-; CHECK-NEXT:    mov r2, r3
-; CHECK-NEXT:  .LBB7_2: @ %entry
-; CHECK-NEXT:    lsls r0, r2, #2
-; CHECK-NEXT:    bx lr
 entry:
   %cmp = icmp ne i32 %a, %b
   %cond = select i1 %cmp, i32 4, i32 0
   ret i32 %cond
+; CHECK-LABEL: test4b:
+; CHECK-NOT: b{{(ne)|(eq)}}
+; CHECK:       subs  r0, r0, r1
+; CHECK-NEXT:  subs  r1, r0, #1
+; CHECK-NEXT:  sbcs  r0, r1
+; CHECK-NEXT:  lsls  r0, r0, #2
 }
-
diff --git a/llvm/test/CodeGen/Thumb/constants.ll b/llvm/test/CodeGen/Thumb/constants.ll
index b1145d7b1d8..7f885009ca2 100644
--- a/llvm/test/CodeGen/Thumb/constants.ll
+++ b/llvm/test/CodeGen/Thumb/constants.ll
@@ -17,3 +17,20 @@ define i32 @mov_and_add() {
 define i32 @mov_and_add2() {
   ret i32 511
 }
+
+; CHECK-T1-LABEL: @test64
+; CHECK-T2-LABEL: @test64
+; CHECK-T1: movs r4, #0
+; CHECK-T1: mvns r5, r4
+; CHECK-T1: mov r0, r5
+; CHECK-T1: subs r0, #15
+; CHECK-T2: subs.w r0, r{{[0-9]+}}, #15
+; CHECK-T2-NEXT: sbc r1, r{{[0-9]+}}, #0
+define i32 @test64() {
+entry:
+  tail call void @fn1(i64 -1)
+  tail call void @fn1(i64 -1)
+  tail call void @fn1(i64 -16)
+  ret i32 0
+}
+declare void @fn1(i64) ;
diff --git a/llvm/test/CodeGen/Thumb/long-setcc.ll b/llvm/test/CodeGen/Thumb/long-setcc.ll
index 1f999f778c9..f077d0e4cf4 100644
--- a/llvm/test/CodeGen/Thumb/long-setcc.ll
+++ b/llvm/test/CodeGen/Thumb/long-setcc.ll
@@ -9,10 +9,9 @@ define i1 @t1(i64 %x) {
 
 define i1 @t2(i64 %x) {
 ; CHECK-LABEL: t2:
-; CHECK: movs    r0, #1
-; CHECK: movs    r2, #0
-; CHECK: cmp     r1, #0
-; CHECK: beq     .LBB1_2
+; CHECK: movs  r0, #0
+; CHECK: subs  r0, r0, r1
+; CHECK: adcs  r0, r1
   %tmp = icmp ult i64 %x, 4294967296
   ret i1 %tmp
 }
@@ -24,5 +23,4 @@ define i1 @t3(i32 %x) {
   ret i1 %tmp
 }
 
-
 ; CHECK-NOT: cmp