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| author | Oliver Stannard <oliver.stannard@arm.com> | 2014-10-01 09:02:17 +0000 |
|---|---|---|
| committer | Oliver Stannard <oliver.stannard@arm.com> | 2014-10-01 09:02:17 +0000 |
| commit | 37e4daab05c9fd2848e0cb55f6e39e9697745b3d (patch) | |
| tree | ebaa61a77b1f51d56719fcd27e87105e43c6d48a /llvm/test/CodeGen/Thumb2/float-intrinsics-float.ll | |
| parent | 79dc4420f0106dbc466f00d806484adc9aa8c630 (diff) | |
| download | bcm5719-llvm-37e4daab05c9fd2848e0cb55f6e39e9697745b3d.tar.gz bcm5719-llvm-37e4daab05c9fd2848e0cb55f6e39e9697745b3d.zip | |
[ARM] Add support for Cortex-M7, FPv5-SP and FPv5-DP (LLVM)
The Cortex-M7 has 3 options for its FPU: none, FPv5-SP-D16 and
FPv5-DP-D16. FPv5 has the same instructions as FP-ARMv8, so it can be
modelled using the same target feature, and all double-precision
operations are already disabled by the fp-only-sp target features.
llvm-svn: 218747
Diffstat (limited to 'llvm/test/CodeGen/Thumb2/float-intrinsics-float.ll')
| -rw-r--r-- | llvm/test/CodeGen/Thumb2/float-intrinsics-float.ll | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/llvm/test/CodeGen/Thumb2/float-intrinsics-float.ll b/llvm/test/CodeGen/Thumb2/float-intrinsics-float.ll index b29ab35c8f6..f811b69bc9e 100644 --- a/llvm/test/CodeGen/Thumb2/float-intrinsics-float.ll +++ b/llvm/test/CodeGen/Thumb2/float-intrinsics-float.ll @@ -1,6 +1,7 @@ ; RUN: llc < %s -mtriple=thumbv7-none-eabi -mcpu=cortex-m3 | FileCheck %s -check-prefix=CHECK -check-prefix=SOFT -check-prefix=NONE ; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m4 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=SP -; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP +; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-m7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=VFP +; RUN: llc < %s -mtriple=thumbv7-none-eabihf -mcpu=cortex-a7 | FileCheck %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=NEON declare float @llvm.sqrt.f32(float %Val) define float @sqrt_f(float %a) { @@ -117,8 +118,10 @@ define float @copysign_f(float %a, float %b) { ; NONE: bfi r{{[0-9]+}}, [[REG]], #31, #1 ; SP: lsrs [[REG:r[0-9]+]], r{{[0-9]+}}, #31 ; SP: bfi r{{[0-9]+}}, [[REG]], #31, #1 -; DP: vmov.i32 [[REG:d[0-9]+]], #0x80000000 -; DP: vbsl [[REG]], d +; VFP: lsrs [[REG:r[0-9]+]], r{{[0-9]+}}, #31 +; VFP: bfi r{{[0-9]+}}, [[REG]], #31, #1 +; NEON: vmov.i32 [[REG:d[0-9]+]], #0x80000000 +; NEON: vbsl [[REG]], d %1 = call float @llvm.copysign.f32(float %a, float %b) ret float %1 } @@ -185,8 +188,9 @@ define float @fmuladd_f(float %a, float %b, float %c) { ; SOFT: bl __aeabi_fmul ; SOFT: bl __aeabi_fadd ; SP: vmla.f32 -; DP: vmul.f32 -; DP: vadd.f32 +; VFP: vmla.f32 +; NEON: vmul.f32 +; NEON: vadd.f32 %1 = call float @llvm.fmuladd.f32(float %a, float %b, float %c) ret float %1 } |
