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| author | Evan Cheng <evan.cheng@apple.com> | 2010-10-29 18:09:28 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-10-29 18:09:28 +0000 |
| commit | 6c1414f9c2084e47ee3d4fcae30d03de72f9ee3f (patch) | |
| tree | f53d79edd7deeaf54d476c206f62c58abe3b0390 /llvm/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll | |
| parent | 0c4c5ca6e1d141e60cafeb136b824293cbd87b4a (diff) | |
| download | bcm5719-llvm-6c1414f9c2084e47ee3d4fcae30d03de72f9ee3f.tar.gz bcm5719-llvm-6c1414f9c2084e47ee3d4fcae30d03de72f9ee3f.zip | |
Avoiding overly aggressive latency scheduling. If the two nodes share an
operand and one of them has a single use that is a live out copy, favor the
one that is live out. Otherwise it will be difficult to eliminate the copy
if the instruction is a loop induction variable update. e.g.
BB:
sub r1, r3, #1
str r0, [r2, r3]
mov r3, r1
cmp
bne BB
=>
BB:
str r0, [r2, r3]
sub r3, r3, #1
cmp
bne BB
This fixed the recent 256.bzip2 regression.
llvm-svn: 117675
Diffstat (limited to 'llvm/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll')
| -rw-r--r-- | llvm/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll b/llvm/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll index ea401ee0e59..c169fb334a3 100644 --- a/llvm/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll +++ b/llvm/test/CodeGen/Thumb2/cross-rc-coalescing-2.ll @@ -15,9 +15,9 @@ bb.nph: ; preds = %bb5 ; Loop preheader ; CHECK: vmov.f32 -; CHECK: vmul.f32 ; CHECK: vsub.f32 ; CHECK: vadd.f32 +; CHECK: vmul.f32 bb7: ; preds = %bb9, %bb.nph %s1.02 = phi float [ undef, %bb.nph ], [ %35, %bb9 ] ; <float> [#uses=3] %tmp79 = add i32 undef, undef ; <i32> [#uses=1] |
