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| author | Oliver Stannard <oliver.stannard@arm.com> | 2014-10-01 09:02:17 +0000 |
|---|---|---|
| committer | Oliver Stannard <oliver.stannard@arm.com> | 2014-10-01 09:02:17 +0000 |
| commit | 37e4daab05c9fd2848e0cb55f6e39e9697745b3d (patch) | |
| tree | ebaa61a77b1f51d56719fcd27e87105e43c6d48a /llvm/test/CodeGen/Thumb2/cortex-fp.ll | |
| parent | 79dc4420f0106dbc466f00d806484adc9aa8c630 (diff) | |
| download | bcm5719-llvm-37e4daab05c9fd2848e0cb55f6e39e9697745b3d.tar.gz bcm5719-llvm-37e4daab05c9fd2848e0cb55f6e39e9697745b3d.zip | |
[ARM] Add support for Cortex-M7, FPv5-SP and FPv5-DP (LLVM)
The Cortex-M7 has 3 options for its FPU: none, FPv5-SP-D16 and
FPv5-DP-D16. FPv5 has the same instructions as FP-ARMv8, so it can be
modelled using the same target feature, and all double-precision
operations are already disabled by the fp-only-sp target features.
llvm-svn: 218747
Diffstat (limited to 'llvm/test/CodeGen/Thumb2/cortex-fp.ll')
| -rw-r--r-- | llvm/test/CodeGen/Thumb2/cortex-fp.ll | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/Thumb2/cortex-fp.ll b/llvm/test/CodeGen/Thumb2/cortex-fp.ll index b4227615af4..5548492ed09 100644 --- a/llvm/test/CodeGen/Thumb2/cortex-fp.ll +++ b/llvm/test/CodeGen/Thumb2/cortex-fp.ll @@ -1,5 +1,6 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -march=thumb -mcpu=cortex-m3 | FileCheck %s -check-prefix=CHECK -check-prefix=CORTEXM3 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -march=thumb -mcpu=cortex-m4 | FileCheck %s -check-prefix=CHECK -check-prefix=CORTEXM4 +; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -march=thumb -mcpu=cortex-m7 | FileCheck %s -check-prefix=CHECK -check-prefix=CORTEXM7 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -march=thumb -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK -check-prefix=CORTEXA8 @@ -8,6 +9,7 @@ entry: ; CHECK-LABEL: foo: ; CORTEXM3: bl ___mulsf3 ; CORTEXM4: vmul.f32 s +; CORTEXM7: vmul.f32 s ; CORTEXA8: vmul.f32 d %0 = fmul float %a, %b ret float %0 @@ -19,6 +21,7 @@ entry: %0 = fmul double %a, %b ; CORTEXM3: bl ___muldf3 ; CORTEXM4: {{bl|b.w}} ___muldf3 +; CORTEXM7: vmul.f64 d ; CORTEXA8: vmul.f64 d ret double %0 } |
