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| author | Artyom Skrobov <Artyom.Skrobov@arm.com> | 2017-04-23 06:58:08 +0000 |
|---|---|---|
| committer | Artyom Skrobov <Artyom.Skrobov@arm.com> | 2017-04-23 06:58:08 +0000 |
| commit | 53cf1897ccea18a5919e109cde61b29d16dd8fb9 (patch) | |
| tree | 33b7af4de530c2e04640e0c8cf03fc0f16f72d81 /llvm/test/CodeGen/Thumb/optionaldef-scheduling.ll | |
| parent | 474e5de72de95414c883fc2759f8a75b20ee42be (diff) | |
| download | bcm5719-llvm-53cf1897ccea18a5919e109cde61b29d16dd8fb9.tar.gz bcm5719-llvm-53cf1897ccea18a5919e109cde61b29d16dd8fb9.zip | |
[ARM] ScheduleDAGRRList::DelayForLiveRegsBottomUp must consider OptionalDefs
Summary:
D30400 has enabled tADC and tSBC instructions to be unglued, thereby allowing CPSR to remain live between Thumb1 scheduling units.
Most Thumb1 instructions have an OptionalDef for CPSR; but the scheduler ignored the OptionalDefs, and could unwittingly insert a flag-setting instruction in between an ADDS and the corresponding ADC.
Reviewers: javed.absar, atrick, MatzeB, t.p.northover, jmolloy, rengolin
Reviewed By: javed.absar
Subscribers: rogfer01, efriedma, aemerson, rengolin, llvm-commits, MatzeB
Differential Revision: https://reviews.llvm.org/D31081
llvm-svn: 301106
Diffstat (limited to 'llvm/test/CodeGen/Thumb/optionaldef-scheduling.ll')
| -rw-r--r-- | llvm/test/CodeGen/Thumb/optionaldef-scheduling.ll | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/Thumb/optionaldef-scheduling.ll b/llvm/test/CodeGen/Thumb/optionaldef-scheduling.ll new file mode 100644 index 00000000000..bd091cf2b6f --- /dev/null +++ b/llvm/test/CodeGen/Thumb/optionaldef-scheduling.ll @@ -0,0 +1,18 @@ +; RUN: llc -mtriple=thumb-eabi %s -verify-machineinstrs -o - | FileCheck %s +; RUN: llc -mtriple=thumbv6-eabi %s -verify-machineinstrs -o - | FileCheck %s + +define i1 @test(i64 %arg) { +entry: + %ispos = icmp sgt i64 %arg, -1 + %neg = sub i64 0, %arg + %sel = select i1 %ispos, i64 %arg, i64 %neg + %cmp2 = icmp eq i64 %sel, %arg + ret i1 %cmp2 +} + +; The scheduler used to ignore OptionalDefs, and could unwittingly insert +; a flag-setting instruction in between an ADDS and the corresponding ADC. + +; CHECK: adds +; CHECK-NOT: eors +; CHECK: adcs |
