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authorRichard Sandiford <rsandifo@linux.vnet.ibm.com>2013-07-11 09:10:09 +0000
committerRichard Sandiford <rsandifo@linux.vnet.ibm.com>2013-07-11 09:10:09 +0000
commitea9b6aa20bf8bd83eddff1b788c33183ea5bbffa (patch)
treee2968b926195711a6c0672d279761fb672c14065 /llvm/test/CodeGen/SystemZ
parent84f54a3bc9067cf9b48584d3da4e71049c490cac (diff)
downloadbcm5719-llvm-ea9b6aa20bf8bd83eddff1b788c33183ea5bbffa.tar.gz
bcm5719-llvm-ea9b6aa20bf8bd83eddff1b788c33183ea5bbffa.zip
[SystemZ] Use zeroing form of RISBG for shift-and-AND sequences
Extend r186072 to handle shifts and ANDs. llvm-svn: 186073
Diffstat (limited to 'llvm/test/CodeGen/SystemZ')
-rw-r--r--llvm/test/CodeGen/SystemZ/fp-move-02.ll4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/SystemZ/fp-move-02.ll b/llvm/test/CodeGen/SystemZ/fp-move-02.ll
index a02c8564125..f828b2d1ad4 100644
--- a/llvm/test/CodeGen/SystemZ/fp-move-02.ll
+++ b/llvm/test/CodeGen/SystemZ/fp-move-02.ll
@@ -16,7 +16,7 @@ define float @f1(i32 %a) {
; surrounding code.
define float @f2(i64 %big) {
; CHECK: f2:
-; CHECK: sllg [[REGISTER:%r[0-5]]], %r2, 31
+; CHECK: risbg [[REGISTER:%r[0-5]]], %r2, 0, 159, 31
; CHECK: ldgr %f0, [[REGISTER]]
%shift = lshr i64 %big, 1
%a = trunc i64 %shift to i32
@@ -27,7 +27,7 @@ define float @f2(i64 %big) {
; Another example of the same thing.
define float @f3(i64 %big) {
; CHECK: f3:
-; CHECK: sllg [[REGISTER:%r[0-5]]], %r2, 2
+; CHECK: risbg [[REGISTER:%r[0-5]]], %r2, 0, 159, 2
; CHECK: ldgr %f0, [[REGISTER]]
%shift = ashr i64 %big, 30
%a = trunc i64 %shift to i32
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