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| author | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-10-17 11:16:57 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-10-17 11:16:57 +0000 |
| commit | 95f7ba988bbc2713bbd13f7410751312e4aebbc9 (patch) | |
| tree | 8b5cd8ba189c3231a0bb974b46fcf93a9cdeaf51 /llvm/test/CodeGen/SystemZ | |
| parent | 561badf717089f5c5afe21afc44a96e9bedf9ec3 (diff) | |
| download | bcm5719-llvm-95f7ba988bbc2713bbd13f7410751312e4aebbc9.tar.gz bcm5719-llvm-95f7ba988bbc2713bbd13f7410751312e4aebbc9.zip | |
Replace sra with srl if a single sign bit is required
E.g. (and (sra (i32 x) 31) 2) -> (and (srl (i32 x) 30) 2).
llvm-svn: 192884
Diffstat (limited to 'llvm/test/CodeGen/SystemZ')
| -rw-r--r-- | llvm/test/CodeGen/SystemZ/shift-10.ll | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/SystemZ/shift-10.ll b/llvm/test/CodeGen/SystemZ/shift-10.ll index 3fd965745ed..46ed2180dfd 100644 --- a/llvm/test/CodeGen/SystemZ/shift-10.ll +++ b/llvm/test/CodeGen/SystemZ/shift-10.ll @@ -64,3 +64,15 @@ define i64 @f5(i32 %a) { %or = or i64 %shl, 7 ret i64 %or } + +; Test that SRA gets replaced with SRL if the sign bit is the only one +; that matters. +define i64 @f6(i64 %a) { +; CHECK-LABEL: f6: +; CHECK: risbg %r2, %r2, 55, 183, 19 +; CHECK: br %r14 + %shl = shl i64 %a, 10 + %shr = ashr i64 %shl, 60 + %and = and i64 %shr, 256 + ret i64 %and +} |
