Followup on Proposal to move MIR physical register namespace to '$' sigil.

Discussed here:

http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html

In preparation for adding support for named vregs we are changing the sigil for
physical registers in MIR to '$' from '%'. This will prevent name clashes of
named physical register with named vregs.

llvm-svn: 323922

11 files changed, 254 insertions, 254 deletions

diff --git a/llvm/test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir b/llvm/test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir
index 163b637e10b..7c0ad081f0c 100644
--- a/llvm/test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir
+++ b/llvm/test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir
@@ -149,52 +149,52 @@ body:             |
     %11 = VGBM 0
     %43 = LHIMux 0
     %44 = LARL %const.0
-    %45 = VL64 %44, 0, %noreg :: (load 8 from constant-pool)
+    %45 = VL64 %44, 0, $noreg :: (load 8 from constant-pool)
   
   bb.1:
     ADJCALLSTACKDOWN 0, 0
     %12 = LZDR
-    %f0d = COPY %12
-    CallBRASL &fmod, killed %f0d, undef %f2d, csr_systemz, implicit-def dead %r14d, implicit-def dead %cc, implicit-def %f0d
+    $f0d = COPY %12
+    CallBRASL &fmod, killed $f0d, undef $f2d, csr_systemz, implicit-def dead $r14d, implicit-def dead $cc, implicit-def $f0d
     ADJCALLSTACKUP 0, 0
-    KILL killed %f0d
+    KILL killed $f0d
   
   bb.2:
-    %17 = VLGVH %11, %noreg, 0
+    %17 = VLGVH %11, $noreg, 0
     %19 = LHR %17.subreg_l32
     undef %20.subreg_l64 = LGHI 0
     %20 = DSGFR %20, %19
-    %22 = VLGVH %11, %noreg, 3
+    %22 = VLGVH %11, $noreg, 3
     %24 = LHR %22.subreg_l32
     undef %25.subreg_l64 = LGHI 0
     %25 = DSGFR %25, %24
-    %31 = VLGVH %11, %noreg, 1
+    %31 = VLGVH %11, $noreg, 1
     %33 = LHR %31.subreg_l32
     undef %34.subreg_l64 = LGHI 0
     %34 = DSGFR %34, %33
-    %37 = VLGVH %11, %noreg, 2
+    %37 = VLGVH %11, $noreg, 2
     %39 = LHR %37.subreg_l32
     undef %40.subreg_l64 = LGHI 0
     %40 = DSGFR %40, %39
-    CHIMux %43, 0, implicit-def %cc
-    BRC 14, 6, %bb.2, implicit killed %cc
+    CHIMux %43, 0, implicit-def $cc
+    BRC 14, 6, %bb.2, implicit killed $cc
     J %bb.3
   
   bb.3:
-    WFCDB undef %46, %45, implicit-def %cc
-    %48 = IPM implicit killed %cc
-    %48 = AFIMux %48, 268435456, implicit-def dead %cc
+    WFCDB undef %46, %45, implicit-def $cc
+    %48 = IPM implicit killed $cc
+    %48 = AFIMux %48, 268435456, implicit-def dead $cc
     %6 = RISBMux undef %6, %48, 31, 159, 35
-    WFCDB undef %50, %45, implicit-def %cc
-    BRC 15, 6, %bb.1, implicit killed %cc
+    WFCDB undef %50, %45, implicit-def $cc
+    BRC 15, 6, %bb.1, implicit killed $cc
     J %bb.4
   
   bb.4:
     %36 = VLVGP %25.subreg_l64, %25.subreg_l64
-    %36 = VLVGH %36, %20.subreg_l32, %noreg, 0
-    %36 = VLVGH %36, %34.subreg_l32, %noreg, 1
-    dead %36 = VLVGH %36, %40.subreg_l32, %noreg, 2
-    %4 = LG undef %42, 0, %noreg :: (load 8 from `i64* undef`)
+    %36 = VLVGH %36, %20.subreg_l32, $noreg, 0
+    %36 = VLVGH %36, %34.subreg_l32, $noreg, 1
+    dead %36 = VLVGH %36, %40.subreg_l32, $noreg, 2
+    %4 = LG undef %42, 0, $noreg :: (load 8 from `i64* undef`)
     undef %57.subreg_h64 = LLILL 0
     undef %66.subreg_h64 = LLILL 0
     undef %79.subreg_h64 = LLILL 0
@@ -204,61 +204,61 @@ body:             |
   bb.5:
   
   bb.6:
-    %51 = VLGVH undef %7, %noreg, 0
+    %51 = VLGVH undef %7, $noreg, 0
     %53 = LLHRMux %51.subreg_l32
-    %54 = VLGVH undef %1, %noreg, 0
+    %54 = VLGVH undef %1, $noreg, 0
     %57.subreg_l32 = LLHRMux %54.subreg_l32
     %58 = COPY %57
     %58 = DLR %58, %53
-    %60 = VLGVH undef %7, %noreg, 3
+    %60 = VLGVH undef %7, $noreg, 3
     %62 = LLHRMux %60.subreg_l32
-    %63 = VLGVH undef %1, %noreg, 3
+    %63 = VLGVH undef %1, $noreg, 3
     %66.subreg_l32 = LLHRMux %63.subreg_l32
     %67 = COPY %66
     %67 = DLR %67, %62
-    %73 = VLGVH undef %7, %noreg, 1
+    %73 = VLGVH undef %7, $noreg, 1
     %75 = LLHRMux %73.subreg_l32
-    %76 = VLGVH undef %1, %noreg, 1
+    %76 = VLGVH undef %1, $noreg, 1
     %79.subreg_l32 = LLHRMux %76.subreg_l32
     %80 = COPY %79
     %80 = DLR %80, %75
-    %83 = VLGVH undef %7, %noreg, 2
+    %83 = VLGVH undef %7, $noreg, 2
     %85 = LLHRMux %83.subreg_l32
-    %86 = VLGVH undef %1, %noreg, 2
+    %86 = VLGVH undef %1, $noreg, 2
     %89.subreg_l32 = LLHRMux %86.subreg_l32
     %90 = COPY %89
     %90 = DLR %90, %85
-    CHIMux %92, 0, implicit-def %cc
-    BRC 14, 6, %bb.7, implicit killed %cc
+    CHIMux %92, 0, implicit-def $cc
+    BRC 14, 6, %bb.7, implicit killed $cc
     J %bb.6
   
   bb.7:
-    CGHI undef %93, 0, implicit-def %cc
-    %96 = IPM implicit killed %cc
-    CGHI undef %97, 0, implicit-def %cc
-    BRC 14, 6, %bb.6, implicit killed %cc
+    CGHI undef %93, 0, implicit-def $cc
+    %96 = IPM implicit killed $cc
+    CGHI undef %97, 0, implicit-def $cc
+    BRC 14, 6, %bb.6, implicit killed $cc
   
   bb.8:
-    CHIMux %6, 0, implicit-def %cc
+    CHIMux %6, 0, implicit-def $cc
     %10 = LLILL 41639
-    dead %10 = LOCGR %10, %4, 14, 6, implicit killed %cc
-    CHIMux %92, 0, implicit-def %cc
-    BRC 14, 6, %bb.5, implicit killed %cc
+    dead %10 = LOCGR %10, %4, 14, 6, implicit killed $cc
+    CHIMux %92, 0, implicit-def $cc
+    BRC 14, 6, %bb.5, implicit killed $cc
     J %bb.9
   
   bb.9:
     %82 = VLVGP %67.subreg_h64, %67.subreg_h64
-    %82 = VLVGH %82, %58.subreg_hl32, %noreg, 0
-    %82 = VLVGH %82, %80.subreg_hl32, %noreg, 1
-    dead %82 = VLVGH %82, %90.subreg_hl32, %noreg, 2
-    %96 = AFIMux %96, 1879048192, implicit-def dead %cc
-    %96 = SRL %96, %noreg, 31
-    dead %11 = VLVGF %11, %96, %noreg, 1
+    %82 = VLVGH %82, %58.subreg_hl32, $noreg, 0
+    %82 = VLVGH %82, %80.subreg_hl32, $noreg, 1
+    dead %82 = VLVGH %82, %90.subreg_hl32, $noreg, 2
+    %96 = AFIMux %96, 1879048192, implicit-def dead $cc
+    %96 = SRL %96, $noreg, 31
+    dead %11 = VLVGF %11, %96, $noreg, 1
     %100 = LHIMux 0
   
   bb.10:
-    CHIMux %100, 0, implicit-def %cc
-    BRC 14, 6, %bb.10, implicit killed %cc
+    CHIMux %100, 0, implicit-def $cc
+    BRC 14, 6, %bb.10, implicit killed $cc
     J %bb.11
   
   bb.11:
diff --git a/llvm/test/CodeGen/SystemZ/clear-liverange-spillreg.mir b/llvm/test/CodeGen/SystemZ/clear-liverange-spillreg.mir
index 06729f0b91a..ac807e8fafa 100644
--- a/llvm/test/CodeGen/SystemZ/clear-liverange-spillreg.mir
+++ b/llvm/test/CodeGen/SystemZ/clear-liverange-spillreg.mir
@@ -162,15 +162,15 @@ body:             |
   bb.0:
     successors: %bb.2(0x00000001), %bb.1(0x7fffffff)
   
-    CHIMux undef %20, 3, implicit-def %cc
-    BRC 14, 8, %bb.2, implicit killed %cc
+    CHIMux undef %20, 3, implicit-def $cc
+    BRC 14, 8, %bb.2, implicit killed $cc
     J %bb.1
   
   bb.1:
     successors: %bb.2(0x00000001), %bb.3(0x7fffffff)
   
-    CHIMux undef %21, 0, implicit-def %cc
-    BRC 14, 6, %bb.3, implicit killed %cc
+    CHIMux undef %21, 0, implicit-def $cc
+    BRC 14, 6, %bb.3, implicit killed $cc
     J %bb.2
   
   bb.2:
@@ -178,15 +178,15 @@ body:             |
   bb.3:
     successors: %bb.6(0x00000001), %bb.4(0x7fffffff)
   
-    CHIMux undef %23, 2, implicit-def %cc
-    BRC 14, 8, %bb.6, implicit killed %cc
+    CHIMux undef %23, 2, implicit-def $cc
+    BRC 14, 8, %bb.6, implicit killed $cc
     J %bb.4
   
   bb.4:
     successors: %bb.5(0x00000001), %bb.7(0x7fffffff)
   
-    CHIMux undef %24, 1, implicit-def %cc
-    BRC 14, 6, %bb.7, implicit killed %cc
+    CHIMux undef %24, 1, implicit-def $cc
+    BRC 14, 6, %bb.7, implicit killed $cc
     J %bb.5
   
   bb.5:
@@ -196,48 +196,48 @@ body:             |
   bb.7:
     successors: %bb.47(0x00000001), %bb.8(0x7fffffff)
   
-    CHIMux undef %25, 1, implicit-def %cc
-    BRC 14, 8, %bb.47, implicit killed %cc
+    CHIMux undef %25, 1, implicit-def $cc
+    BRC 14, 8, %bb.47, implicit killed $cc
     J %bb.8
   
   bb.8:
     successors: %bb.46(0x00000001), %bb.48(0x7fffffff)
   
-    CHIMux undef %26, 2, implicit-def %cc
-    BRC 14, 8, %bb.46, implicit killed %cc
+    CHIMux undef %26, 2, implicit-def $cc
+    BRC 14, 8, %bb.46, implicit killed $cc
     J %bb.48
   
   bb.9:
     successors: %bb.36(0x00000001), %bb.10(0x7fffffff)
   
-    CHIMux undef %31, 1, implicit-def %cc
-    BRC 14, 8, %bb.36, implicit killed %cc
+    CHIMux undef %31, 1, implicit-def $cc
+    BRC 14, 8, %bb.36, implicit killed $cc
     J %bb.10
   
   bb.10:
     successors: %bb.35(0x00000001), %bb.37(0x7fffffff)
   
-    CHIMux undef %32, 2, implicit-def %cc
-    BRC 14, 8, %bb.35, implicit killed %cc
+    CHIMux undef %32, 2, implicit-def $cc
+    BRC 14, 8, %bb.35, implicit killed $cc
     J %bb.37
   
   bb.11:
     %4 = COPY %60
-    %6 = SLLG %120, %noreg, 1
+    %6 = SLLG %120, $noreg, 1
     %7 = LA %6, 64, %41
-    %6 = AGR %6, %42, implicit-def dead %cc
-    %45 = SRLK %120.subreg_l32, %noreg, 31
-    %45 = AR %45, %120.subreg_l32, implicit-def dead %cc
-    %45 = NIFMux %45, 536870910, implicit-def dead %cc
-    %47 = SRK %120.subreg_l32, %45, implicit-def dead %cc
-    %47 = SLL %47, %noreg, 3
+    %6 = AGR %6, %42, implicit-def dead $cc
+    %45 = SRLK %120.subreg_l32, $noreg, 31
+    %45 = AR %45, %120.subreg_l32, implicit-def dead $cc
+    %45 = NIFMux %45, 536870910, implicit-def dead $cc
+    %47 = SRK %120.subreg_l32, %45, implicit-def dead $cc
+    %47 = SLL %47, $noreg, 3
     %81 = LGFR %47
   
   bb.12:
     successors: %bb.56, %bb.13
   
-    CHIMux %38, 0, implicit-def %cc
-    BRC 14, 8, %bb.13, implicit killed %cc
+    CHIMux %38, 0, implicit-def $cc
+    BRC 14, 8, %bb.13, implicit killed $cc
   
   bb.56:
     J %bb.16
@@ -247,24 +247,24 @@ body:             |
   
     ADJCALLSTACKDOWN 0, 0
     %49 = LGFR %120.subreg_l32
-    %r2d = COPY %49
-    CallBRASL @Get_Direct_Cost8x8, killed %r2d, undef %r3d, csr_systemz, implicit-def dead %r14d, implicit-def dead %cc, implicit-def %r2d
+    $r2d = COPY %49
+    CallBRASL @Get_Direct_Cost8x8, killed $r2d, undef $r3d, csr_systemz, implicit-def dead $r14d, implicit-def dead $cc, implicit-def $r2d
     ADJCALLSTACKUP 0, 0
-    %51 = COPY killed %r2d
+    %51 = COPY killed $r2d
     MVHHI %7, 0, 0 :: (store 2)
-    %12 = ARK %51.subreg_l32, %125, implicit-def dead %cc
-    CFIMux %51.subreg_l32, 2147483647, implicit-def %cc
-    %12 = LOCRMux %12, %126, 14, 8, implicit killed %cc
-    CFIMux %125, 2147483647, implicit-def %cc
-    %12 = LOCRMux %12, %126, 14, 8, implicit killed %cc
-    CHIMux undef %56, 0, implicit-def %cc
-    BRC 14, 6, %bb.15, implicit killed %cc
+    %12 = ARK %51.subreg_l32, %125, implicit-def dead $cc
+    CFIMux %51.subreg_l32, 2147483647, implicit-def $cc
+    %12 = LOCRMux %12, %126, 14, 8, implicit killed $cc
+    CFIMux %125, 2147483647, implicit-def $cc
+    %12 = LOCRMux %12, %126, 14, 8, implicit killed $cc
+    CHIMux undef %56, 0, implicit-def $cc
+    BRC 14, 6, %bb.15, implicit killed $cc
     J %bb.14
   
   bb.14:
-    %124 = AHIMux %124, 1, implicit-def dead %cc
+    %124 = AHIMux %124, 1, implicit-def dead $cc
     ADJCALLSTACKDOWN 0, 0
-    CallBRASL @store_coding_state, undef %r2d, csr_systemz, implicit-def dead %r14d, implicit-def dead %cc
+    CallBRASL @store_coding_state, undef $r2d, csr_systemz, implicit-def dead $r14d, implicit-def dead $cc
     ADJCALLSTACKUP 0, 0
     %125 = COPY %12
     J %bb.16
@@ -274,8 +274,8 @@ body:             |
   bb.16:
     successors: %bb.12(0x7c000000), %bb.17(0x04000000)
   
-    CLGFI undef %59, 4, implicit-def %cc
-    BRC 14, 4, %bb.12, implicit killed %cc
+    CLGFI undef %59, 4, implicit-def $cc
+    BRC 14, 4, %bb.12, implicit killed $cc
     J %bb.17
   
   bb.17:
@@ -283,44 +283,44 @@ body:             |
   
     MVHI %0, 332, 2 :: (store 4)
     %60 = COPY %126
-    %60 = AR %60, %4, implicit-def dead %cc
-    %18 = LHMux %6, 0, %noreg :: (load 2)
-    CHIMux %38, 0, implicit-def %cc
-    BRC 14, 6, %bb.19, implicit killed %cc
+    %60 = AR %60, %4, implicit-def dead $cc
+    %18 = LHMux %6, 0, $noreg :: (load 2)
+    CHIMux %38, 0, implicit-def $cc
+    BRC 14, 6, %bb.19, implicit killed $cc
     J %bb.18
   
   bb.18:
-    %62 = SLLG %81, %noreg, 1
+    %62 = SLLG %81, $noreg, 1
     %64 = LA %62, 0, %63
-    %65 = LG undef %66, 0, %noreg :: (load 8)
-    %67 = LGF undef %68, 0, %noreg :: (load 4)
+    %65 = LG undef %66, 0, $noreg :: (load 8)
+    %67 = LGF undef %68, 0, $noreg :: (load 4)
     MVC undef %69, 0, 2, %64, 0 :: (store 2), (load 2)
     %70 = COPY %81
-    %70 = OILL64 %70, 3, implicit-def dead %cc
-    %71 = LA %70, 2, %noreg
-    %72 = SLLG %71, %noreg, 1
+    %70 = OILL64 %70, 3, implicit-def dead $cc
+    %71 = LA %70, 2, $noreg
+    %72 = SLLG %71, $noreg, 1
     %73 = LHMux %72, 0, %63 :: (load 2)
     %74 = LA %70, 2, %67
-    %75 = SLLG %74, %noreg, 1
-    %76 = LG %65, 0, %noreg :: (load 8)
+    %75 = SLLG %74, $noreg, 1
+    %76 = LG %65, 0, $noreg :: (load 8)
     STHMux %73, %76, 0, %75 :: (store 2)
-    %77 = LG undef %78, 0, %noreg :: (load 8)
+    %77 = LG undef %78, 0, $noreg :: (load 8)
     %79 = LHRL @rec_mbY8x8 :: (load 2)
-    STHMux %79, %77, 0, %noreg :: (store 2)
+    STHMux %79, %77, 0, $noreg :: (store 2)
     %80 = LHMux %72, 0, %63 :: (load 2)
     STHMux %80, %77, 0, %75 :: (store 2)
-    %81 = OILL64 %81, 7, implicit-def dead %cc
-    %82 = SLLG %81, %noreg, 1
+    %81 = OILL64 %81, 7, implicit-def dead $cc
+    %82 = SLLG %81, $noreg, 1
     %83 = LHMux %82, 0, %63 :: (load 2)
-    STHMux %83, %77, 0, %noreg :: (store 2)
+    STHMux %83, %77, 0, $noreg :: (store 2)
     %84 = LA %62, 64, %63
     MVC undef %85, 0, 2, %84, 0 :: (store 2), (load 2)
-    %86 = SLLG %70, %noreg, 1
+    %86 = SLLG %70, $noreg, 1
     %87 = LHMux %86, 64, %63 :: (load 2)
-    %88 = SLLG %67, %noreg, 3
+    %88 = SLLG %67, $noreg, 3
     %89 = LG %65, 16, %88 :: (load 8)
     %90 = LA %70, 0, %67
-    %91 = SLLG %90, %noreg, 1
+    %91 = SLLG %90, $noreg, 1
     STHMux %87, %89, 0, %91 :: (store 2)
     %92 = LA %72, 64, %63
     MVC undef %93, 0, 2, %92, 0 :: (store 2), (load 2)
@@ -332,39 +332,39 @@ body:             |
   bb.19:
     successors: %bb.20(0x04000000), %bb.11(0x7c000000)
   
-    %98 = LGH %7, 0, %noreg :: (load 2)
-    %99 = LGH undef %100, 0, %noreg :: (load 2)
+    %98 = LGH %7, 0, $noreg :: (load 2)
+    %99 = LGH undef %100, 0, $noreg :: (load 2)
     ADJCALLSTACKDOWN 0, 0
     %101 = LGFR %120.subreg_l32
     %102 = LGFR %18
-    %r2d = COPY %101
-    %r3d = COPY %102
-    %r4d = LGHI 0
-    %r5d = COPY %98
-    %r6d = COPY %99
-    CallBRASL @SetRefAndMotionVectors, killed %r2d, killed %r3d, killed %r4d, killed %r5d, killed %r6d, csr_systemz, implicit-def dead %r14d, implicit-def dead %cc
+    $r2d = COPY %101
+    $r3d = COPY %102
+    $r4d = LGHI 0
+    $r5d = COPY %98
+    $r6d = COPY %99
+    CallBRASL @SetRefAndMotionVectors, killed $r2d, killed $r3d, killed $r4d, killed $r5d, killed $r6d, csr_systemz, implicit-def dead $r14d, implicit-def dead $cc
     ADJCALLSTACKUP 0, 0
     ADJCALLSTACKDOWN 0, 0
-    CallBRASL @reset_coding_state, undef %r2d, csr_systemz, implicit-def dead %r14d, implicit-def dead %cc
+    CallBRASL @reset_coding_state, undef $r2d, csr_systemz, implicit-def dead $r14d, implicit-def dead $cc
     ADJCALLSTACKUP 0, 0
-    %120 = LA %120, 1, %noreg
-    CGHI %120, 4, implicit-def %cc
-    BRC 14, 6, %bb.11, implicit killed %cc
+    %120 = LA %120, 1, $noreg
+    CGHI %120, 4, implicit-def $cc
+    BRC 14, 6, %bb.11, implicit killed $cc
     J %bb.20
   
   bb.20:
     successors: %bb.22(0x00000001), %bb.21(0x7fffffff)
   
     MVHI undef %105, 0, 0 :: (store 4)
-    CHIMux undef %106, 3, implicit-def %cc
-    BRC 14, 8, %bb.22, implicit killed %cc
+    CHIMux undef %106, 3, implicit-def $cc
+    BRC 14, 8, %bb.22, implicit killed $cc
     J %bb.21
   
   bb.21:
     successors: %bb.22(0x00000001), %bb.23(0x7fffffff)
   
-    CHIMux undef %107, 0, implicit-def %cc
-    BRC 14, 6, %bb.23, implicit killed %cc
+    CHIMux undef %107, 0, implicit-def $cc
+    BRC 14, 6, %bb.23, implicit killed $cc
     J %bb.22
   
   bb.22:
@@ -373,21 +373,21 @@ body:             |
     successors: %bb.26(0x00000001), %bb.24(0x7fffffff)
   
     ADJCALLSTACKDOWN 0, 0
-    CallBRASL @Get_Direct_CostMB, undef %f0d, csr_systemz, implicit-def dead %r14d, implicit-def dead %cc, implicit-def dead %r2d
+    CallBRASL @Get_Direct_CostMB, undef $f0d, csr_systemz, implicit-def dead $r14d, implicit-def dead $cc, implicit-def dead $r2d
     ADJCALLSTACKUP 0, 0
     ADJCALLSTACKDOWN 0, 0
-    %r2d = LGHI 0
-    CallBRASL @SetModesAndRefframeForBlocks, killed %r2d, csr_systemz, implicit-def dead %r14d, implicit-def dead %cc
+    $r2d = LGHI 0
+    CallBRASL @SetModesAndRefframeForBlocks, killed $r2d, csr_systemz, implicit-def dead $r14d, implicit-def dead $cc
     ADJCALLSTACKUP 0, 0
-    CHIMux undef %111, 13, implicit-def %cc
-    BRC 14, 8, %bb.26, implicit killed %cc
+    CHIMux undef %111, 13, implicit-def $cc
+    BRC 14, 8, %bb.26, implicit killed $cc
     J %bb.24
   
   bb.24:
     successors: %bb.25(0x00000001), %bb.27(0x7fffffff)
   
-    CHIMux undef %112, 8, implicit-def %cc
-    BRC 14, 6, %bb.27, implicit killed %cc
+    CHIMux undef %112, 8, implicit-def $cc
+    BRC 14, 6, %bb.27, implicit killed $cc
     J %bb.25
   
   bb.25:
@@ -397,8 +397,8 @@ body:             |
   bb.27:
     successors: %bb.28, %bb.29
   
-    CHIMux undef %114, 0, implicit-def %cc
-    BRC 14, 6, %bb.29, implicit killed %cc
+    CHIMux undef %114, 0, implicit-def $cc
+    BRC 14, 6, %bb.29, implicit killed $cc
   
   bb.28:
     %130 = CDFBR %60
@@ -410,16 +410,16 @@ body:             |
   bb.30:
     successors: %bb.33(0x00000001), %bb.31(0x7fffffff)
   
-    VST64 %130, undef %117, 0, %noreg :: (store 8)
-    CHIMux undef %118, 2, implicit-def %cc
-    BRC 14, 8, %bb.33, implicit killed %cc
+    VST64 %130, undef %117, 0, $noreg :: (store 8)
+    CHIMux undef %118, 2, implicit-def $cc
+    BRC 14, 8, %bb.33, implicit killed $cc
     J %bb.31
   
   bb.31:
     successors: %bb.32(0x00000001), %bb.34(0x7fffffff)
   
-    CHIMux undef %119, 1, implicit-def %cc
-    BRC 14, 6, %bb.34, implicit killed %cc
+    CHIMux undef %119, 1, implicit-def $cc
+    BRC 14, 6, %bb.34, implicit killed $cc
     J %bb.32
   
   bb.32:
@@ -436,15 +436,15 @@ body:             |
   bb.37:
     successors: %bb.40(0x00000001), %bb.38(0x7fffffff)
   
-    CHIMux undef %33, 1, implicit-def %cc
-    BRC 14, 8, %bb.40, implicit killed %cc
+    CHIMux undef %33, 1, implicit-def $cc
+    BRC 14, 8, %bb.40, implicit killed $cc
     J %bb.38
   
   bb.38:
     successors: %bb.39(0x00000001), %bb.41(0x7fffffff)
   
-    CHIMux undef %34, 2, implicit-def %cc
-    BRC 14, 6, %bb.41, implicit killed %cc
+    CHIMux undef %34, 2, implicit-def $cc
+    BRC 14, 6, %bb.41, implicit killed $cc
     J %bb.39
   
   bb.39:
@@ -454,15 +454,15 @@ body:             |
   bb.41:
     successors: %bb.44(0x00000001), %bb.42(0x7fffffff)
   
-    CHIMux undef %35, 1, implicit-def %cc
-    BRC 14, 8, %bb.44, implicit killed %cc
+    CHIMux undef %35, 1, implicit-def $cc
+    BRC 14, 8, %bb.44, implicit killed $cc
     J %bb.42
   
   bb.42:
     successors: %bb.43(0x00000001), %bb.45(0x7fffffff)
   
-    CHIMux undef %36, 2, implicit-def %cc
-    BRC 14, 6, %bb.45, implicit killed %cc
+    CHIMux undef %36, 2, implicit-def $cc
+    BRC 14, 6, %bb.45, implicit killed $cc
     J %bb.43
   
   bb.43:
@@ -470,7 +470,7 @@ body:             |
   bb.44:
   
   bb.45:
-    %0 = LG undef %22, 0, %noreg :: (load 8)
+    %0 = LG undef %22, 0, $noreg :: (load 8)
     %38 = LHIMux 0
     STRL %38, @bi_pred_me :: (store 4)
     %120 = LGHI 0
@@ -490,15 +490,15 @@ body:             |
   bb.48:
     successors: %bb.51(0x00000001), %bb.49(0x7fffffff)
   
-    CHIMux undef %27, 1, implicit-def %cc
-    BRC 14, 8, %bb.51, implicit killed %cc
+    CHIMux undef %27, 1, implicit-def $cc
+    BRC 14, 8, %bb.51, implicit killed $cc
     J %bb.49
   
   bb.49:
     successors: %bb.50(0x00000001), %bb.52(0x7fffffff)
   
-    CHIMux undef %28, 2, implicit-def %cc
-    BRC 14, 6, %bb.52, implicit killed %cc
+    CHIMux undef %28, 2, implicit-def $cc
+    BRC 14, 6, %bb.52, implicit killed $cc
     J %bb.50
   
   bb.50:
@@ -508,15 +508,15 @@ body:             |
   bb.52:
     successors: %bb.55(0x00000001), %bb.53(0x7fffffff)
   
-    CHIMux undef %29, 1, implicit-def %cc
-    BRC 14, 8, %bb.55, implicit killed %cc
+    CHIMux undef %29, 1, implicit-def $cc
+    BRC 14, 8, %bb.55, implicit killed $cc
     J %bb.53
   
   bb.53:
     successors: %bb.54(0x00000001), %bb.9(0x7fffffff)
   
-    CHIMux undef %30, 2, implicit-def %cc
-    BRC 14, 6, %bb.9, implicit killed %cc
+    CHIMux undef %30, 2, implicit-def $cc
+    BRC 14, 6, %bb.9, implicit killed $cc
     J %bb.54
   
   bb.54:
diff --git a/llvm/test/CodeGen/SystemZ/cond-move-04.mir b/llvm/test/CodeGen/SystemZ/cond-move-04.mir
index e633c81d930..5651c6bdc1e 100644
--- a/llvm/test/CodeGen/SystemZ/cond-move-04.mir
+++ b/llvm/test/CodeGen/SystemZ/cond-move-04.mir
@@ -61,14 +61,14 @@ body:             |
     %5 = LHIMux 10
   
   bb.1 (%ir-block.2):
-    CHIMux %3, 0, implicit-def %cc
-    %0 = LOCRMux undef %0, %5, 14, 6, implicit %cc
-    %0 = LOCRMux %0, %2, 14, 6, implicit killed %cc
+    CHIMux %3, 0, implicit-def $cc
+    %0 = LOCRMux undef %0, %5, 14, 6, implicit $cc
+    %0 = LOCRMux %0, %2, 14, 6, implicit killed $cc
     ADJCALLSTACKDOWN 0, 0
     %7 = LGFR %0
-    %r3d = LGHI 0
-    %r4d = COPY %7
-    CallBRASL @foo, undef %r2d, killed %r3d, killed %r4d, csr_systemz, implicit-def dead %r14d, implicit-def dead %cc, implicit-def dead %r2d
+    $r3d = LGHI 0
+    $r4d = COPY %7
+    CallBRASL @foo, undef $r2d, killed $r3d, killed $r4d, csr_systemz, implicit-def dead $r14d, implicit-def dead $cc, implicit-def dead $r2d
     ADJCALLSTACKUP 0, 0
     J %bb.1
 
diff --git a/llvm/test/CodeGen/SystemZ/cond-move-05.mir b/llvm/test/CodeGen/SystemZ/cond-move-05.mir
index 078913053e6..95507c9e765 100644
--- a/llvm/test/CodeGen/SystemZ/cond-move-05.mir
+++ b/llvm/test/CodeGen/SystemZ/cond-move-05.mir
@@ -67,10 +67,10 @@ body:             |
     undef %3.subreg_l64:gr128bit = LGHI 1
     %3.subreg_h64:gr128bit = LLILL 0
     %3:gr128bit = DLGR %3, %0
-    CLFIMux %3.subreg_hl32, 3631842929, implicit-def %cc
-    %6:grx32bit = LOCRMux undef %6, %3.subreg_hl32, 14, 4, implicit killed %cc
-    CHIMux %6, 0, implicit-def %cc
-    BRC 14, 8, %bb.2.for.inc591.1.i.i, implicit killed %cc
+    CLFIMux %3.subreg_hl32, 3631842929, implicit-def $cc
+    %6:grx32bit = LOCRMux undef %6, %3.subreg_hl32, 14, 4, implicit killed $cc
+    CHIMux %6, 0, implicit-def $cc
+    BRC 14, 8, %bb.2.for.inc591.1.i.i, implicit killed $cc
     J %bb.1.cleanup584.i.i
   
   bb.1.cleanup584.i.i:
diff --git a/llvm/test/CodeGen/SystemZ/fp-cmp-07.mir b/llvm/test/CodeGen/SystemZ/fp-cmp-07.mir
index a297b251145..6df4b2bb017 100644
--- a/llvm/test/CodeGen/SystemZ/fp-cmp-07.mir
+++ b/llvm/test/CodeGen/SystemZ/fp-cmp-07.mir
@@ -24,21 +24,21 @@
 name:            f15
 tracksRegLiveness: true
 liveins:
-  - { reg: '%f0s', virtual-reg: '' }
-  - { reg: '%r2d', virtual-reg: '' }
+  - { reg: '$f0s', virtual-reg: '' }
+  - { reg: '$r2d', virtual-reg: '' }
 body:             |
   bb.0.entry:
-    liveins: %f0s, %r2d
+    liveins: $f0s, $r2d
 
-    LTEBRCompare %f0s, %f0s, implicit-def %cc
-    %f2s = LER %f0s
-    INLINEASM &"blah $0", 1, 9, %f2s
-    CondReturn 15, 4, implicit %f0s, implicit %cc
+    LTEBRCompare $f0s, $f0s, implicit-def $cc
+    $f2s = LER $f0s
+    INLINEASM &"blah $0", 1, 9, $f2s
+    CondReturn 15, 4, implicit $f0s, implicit $cc
 
   bb.1.store:
-    liveins: %f0s, %r2d
+    liveins: $f0s, $r2d
 
-    STE %f0s, killed %r2d, 0, %noreg :: (store 4 into %ir.dest)
-    Return implicit %f0s
+    STE $f0s, killed $r2d, 0, $noreg :: (store 4 into %ir.dest)
+    Return implicit $f0s
 
 ...
diff --git a/llvm/test/CodeGen/SystemZ/fp-conv-17.mir b/llvm/test/CodeGen/SystemZ/fp-conv-17.mir
index 17a5fe24b1d..af5dee19bbe 100644
--- a/llvm/test/CodeGen/SystemZ/fp-conv-17.mir
+++ b/llvm/test/CodeGen/SystemZ/fp-conv-17.mir
@@ -121,82 +121,82 @@ registers:
   - { id: 34, class: fp64bit }
   - { id: 35, class: fp64bit }
 liveins:         
-  - { reg: '%r2d', virtual-reg: '%0' }
-  - { reg: '%r3d', virtual-reg: '%1' }
+  - { reg: '$r2d', virtual-reg: '%0' }
+  - { reg: '$r3d', virtual-reg: '%1' }
 body:             |
   bb.0 (%ir-block.0):
-    liveins: %r2d, %r3d
+    liveins: $r2d, $r3d
   
-    %1 = COPY %r3d
-    %0 = COPY %r2d
-    %2 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
-    %3 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
-    %4 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
-    %5 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
-    %6 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
-    %7 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
-    %8 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
-    %9 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
-    %10 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
-    %11 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
-    %12 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
-    %13 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
-    %14 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
-    %15 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
-    %16 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
-    %17 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
-    %18 = LE %1, 0, %noreg :: (volatile load 4 from %ir.ptr2)
-    STE %2, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
-    STE %3, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
-    STE %4, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
-    STE %5, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
-    STE %6, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
-    STE %7, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
-    STE %8, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
-    STE %9, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
-    STE %10, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
-    STE %11, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
-    STE %12, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
-    STE %13, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
-    STE %14, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
-    STE %15, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
-    STE %16, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
-    STE %17, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
-    STE %18, %1, 0, %noreg :: (volatile store 4 into %ir.ptr2)
+    %1 = COPY $r3d
+    %0 = COPY $r2d
+    %2 = LE %1, 0, $noreg :: (volatile load 4 from %ir.ptr2)
+    %3 = LE %1, 0, $noreg :: (volatile load 4 from %ir.ptr2)
+    %4 = LE %1, 0, $noreg :: (volatile load 4 from %ir.ptr2)
+    %5 = LE %1, 0, $noreg :: (volatile load 4 from %ir.ptr2)
+    %6 = LE %1, 0, $noreg :: (volatile load 4 from %ir.ptr2)
+    %7 = LE %1, 0, $noreg :: (volatile load 4 from %ir.ptr2)
+    %8 = LE %1, 0, $noreg :: (volatile load 4 from %ir.ptr2)
+    %9 = LE %1, 0, $noreg :: (volatile load 4 from %ir.ptr2)
+    %10 = LE %1, 0, $noreg :: (volatile load 4 from %ir.ptr2)
+    %11 = LE %1, 0, $noreg :: (volatile load 4 from %ir.ptr2)
+    %12 = LE %1, 0, $noreg :: (volatile load 4 from %ir.ptr2)
+    %13 = LE %1, 0, $noreg :: (volatile load 4 from %ir.ptr2)
+    %14 = LE %1, 0, $noreg :: (volatile load 4 from %ir.ptr2)
+    %15 = LE %1, 0, $noreg :: (volatile load 4 from %ir.ptr2)
+    %16 = LE %1, 0, $noreg :: (volatile load 4 from %ir.ptr2)
+    %17 = LE %1, 0, $noreg :: (volatile load 4 from %ir.ptr2)
+    %18 = LE %1, 0, $noreg :: (volatile load 4 from %ir.ptr2)
+    STE %2, %1, 0, $noreg :: (volatile store 4 into %ir.ptr2)
+    STE %3, %1, 0, $noreg :: (volatile store 4 into %ir.ptr2)
+    STE %4, %1, 0, $noreg :: (volatile store 4 into %ir.ptr2)
+    STE %5, %1, 0, $noreg :: (volatile store 4 into %ir.ptr2)
+    STE %6, %1, 0, $noreg :: (volatile store 4 into %ir.ptr2)
+    STE %7, %1, 0, $noreg :: (volatile store 4 into %ir.ptr2)
+    STE %8, %1, 0, $noreg :: (volatile store 4 into %ir.ptr2)
+    STE %9, %1, 0, $noreg :: (volatile store 4 into %ir.ptr2)
+    STE %10, %1, 0, $noreg :: (volatile store 4 into %ir.ptr2)
+    STE %11, %1, 0, $noreg :: (volatile store 4 into %ir.ptr2)
+    STE %12, %1, 0, $noreg :: (volatile store 4 into %ir.ptr2)
+    STE %13, %1, 0, $noreg :: (volatile store 4 into %ir.ptr2)
+    STE %14, %1, 0, $noreg :: (volatile store 4 into %ir.ptr2)
+    STE %15, %1, 0, $noreg :: (volatile store 4 into %ir.ptr2)
+    STE %16, %1, 0, $noreg :: (volatile store 4 into %ir.ptr2)
+    STE %17, %1, 0, $noreg :: (volatile store 4 into %ir.ptr2)
+    STE %18, %1, 0, $noreg :: (volatile store 4 into %ir.ptr2)
     %19 = LDEBR %2
-    STD %19, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
+    STD %19, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
     %20 = LDEBR %3
-    STD %20, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
+    STD %20, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
     %21 = LDEBR %4
-    STD %21, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
+    STD %21, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
     %22 = LDEBR %5
-    STD %22, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
+    STD %22, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
     %23 = LDEBR %6
-    STD %23, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
+    STD %23, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
     %24 = LDEBR %7
-    STD %24, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
+    STD %24, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
     %25 = LDEBR %8
-    STD %25, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
+    STD %25, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
     %26 = LDEBR %9
-    STD %26, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
+    STD %26, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
     %27 = LDEBR %10
-    STD %27, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
+    STD %27, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
     %28 = LDEBR %11
-    STD %28, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
+    STD %28, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
     %29 = LDEBR %12
-    STD %29, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
+    STD %29, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
     %30 = LDEBR %13
-    STD %30, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
+    STD %30, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
     %31 = LDEBR %14
-    STD %31, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
+    STD %31, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
     %32 = LDEBR %15
-    STD %32, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
+    STD %32, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
     %33 = LDEBR %16
-    STD %33, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
+    STD %33, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
     %34 = LDEBR %17
-    STD %34, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
+    STD %34, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
     %35 = LDEBR %18
-    STD %35, %0, 0, %noreg :: (volatile store 8 into %ir.ptr1)
+    STD %35, %0, 0, $noreg :: (volatile store 8 into %ir.ptr1)
     Return
 
 ...
diff --git a/llvm/test/CodeGen/SystemZ/load-and-test.mir b/llvm/test/CodeGen/SystemZ/load-and-test.mir
index da01dbc79a9..c83291376e1 100644
--- a/llvm/test/CodeGen/SystemZ/load-and-test.mir
+++ b/llvm/test/CodeGen/SystemZ/load-and-test.mir
@@ -13,18 +13,18 @@ name:            fun0
 tracksRegLiveness: true
 body:             |
   bb.0 ():
-    liveins: %r1d
-    renamable %r0l = L %r1d, 0, %noreg
-    CLFIMux killed renamable %r0l, 0, implicit-def %cc
-    BRC 14, 10, %bb.2, implicit %cc
+    liveins: $r1d
+    renamable $r0l = L $r1d, 0, $noreg
+    CLFIMux killed renamable $r0l, 0, implicit-def $cc
+    BRC 14, 10, %bb.2, implicit $cc
 
   bb.1 ():
-    liveins: %r0l
-    ST killed renamable %r0l, %r15d, 164, %noreg
+    liveins: $r0l
+    ST killed renamable $r0l, $r15d, 164, $noreg
 
   bb.2 ():
-    liveins: %r0l
-    ST killed renamable %r0l, %r15d, 164, %noreg
+    liveins: $r0l
+    ST killed renamable $r0l, $r15d, 164, $noreg
     Return
 ...
 
@@ -36,17 +36,17 @@ name:            fun1
 tracksRegLiveness: true
 body:             |
   bb.0 ():
-    liveins: %r1d
-    renamable %r0l = L %r1d, 0, %noreg
-    CLFIMux killed renamable %r0l, 0, implicit-def %cc
-    BRC 14, 8, %bb.2, implicit %cc
+    liveins: $r1d
+    renamable $r0l = L $r1d, 0, $noreg
+    CLFIMux killed renamable $r0l, 0, implicit-def $cc
+    BRC 14, 8, %bb.2, implicit $cc
 
   bb.1 ():
-    liveins: %r0l
-    ST killed renamable %r0l, %r15d, 164, %noreg
+    liveins: $r0l
+    ST killed renamable $r0l, $r15d, 164, $noreg
 
   bb.2 ():
-    liveins: %r0l
-    ST killed renamable %r0l, %r15d, 164, %noreg
+    liveins: $r0l
+    ST killed renamable $r0l, $r15d, 164, $noreg
     Return
 ...
diff --git a/llvm/test/CodeGen/SystemZ/lower-copy-undef-src.mir b/llvm/test/CodeGen/SystemZ/lower-copy-undef-src.mir
index 322460d79d6..2db796c66b6 100644
--- a/llvm/test/CodeGen/SystemZ/lower-copy-undef-src.mir
+++ b/llvm/test/CodeGen/SystemZ/lower-copy-undef-src.mir
@@ -5,10 +5,10 @@
 # dropped.
 ---
 # CHECK-LABEL: name: undef_copy
-# CHECK: %r13d = KILL undef %r0d, implicit killed %r12q, implicit-def %r12q
+# CHECK: $r13d = KILL undef $r0d, implicit killed $r12q, implicit-def $r12q
 name: undef_copy
 tracksRegLiveness: true
 body: |
   bb.0:
-    liveins: %r12q
-    %r13d = COPY undef %r0d, implicit killed %r12q, implicit-def %r12q
+    liveins: $r12q
+    $r13d = COPY undef $r0d, implicit killed $r12q, implicit-def $r12q
diff --git a/llvm/test/CodeGen/SystemZ/pr32505.ll b/llvm/test/CodeGen/SystemZ/pr32505.ll
index c164592b509..0cf6b67f0a2 100644
--- a/llvm/test/CodeGen/SystemZ/pr32505.ll
+++ b/llvm/test/CodeGen/SystemZ/pr32505.ll
@@ -10,8 +10,8 @@ define <2 x float> @pr32505(<2 x i8> * %a) {
 ; CHECK-NEXT:    lbh %r1, 0(%r2)
 ; CHECK-NEXT:    ldgr %f0, %r1
 ; CHECK-NEXT:    ldgr %f2, %r0
-; CHECK-NEXT:    # kill: def %f0s killed %f0s killed %f0d
-; CHECK-NEXT:    # kill: def %f2s killed %f2s killed %f2d
+; CHECK-NEXT:    # kill: def $f0s killed $f0s killed $f0d
+; CHECK-NEXT:    # kill: def $f2s killed $f2s killed $f2d
 ; CHECK-NEXT:    br %r14
   %L17 = load <2 x i8>, <2 x i8>* %a
   %Se21 = sext <2 x i8> %L17 to <2 x i32>
diff --git a/llvm/test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir b/llvm/test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir
index 29173d1274c..3956ce99623 100644
--- a/llvm/test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir
+++ b/llvm/test/CodeGen/SystemZ/regalloc-fast-invalid-kill-flag.mir
@@ -17,18 +17,18 @@ registers:
   - { id: 0, class: gr128bit }
   - { id: 1, class: gr64bit }
   - { id: 2, class: addr64bit }
-# CHECK: %r0q = L128
-# CHECK-NEXT: %r0l = COPY renamable %r1l
+# CHECK: $r0q = L128
+# CHECK-NEXT: $r0l = COPY renamable $r1l
 # Although R0L partially redefines R0Q, it must not mark R0Q as kill
 # because R1D is still live through that instruction.
-# CHECK-NOT: implicit killed %r0q
-# CHECK-NEXT: %r2d = COPY renamable %r1d
+# CHECK-NOT: implicit killed $r0q
+# CHECK-NEXT: $r2d = COPY renamable $r1d
 # CHECK-NEXT: LARL
 body:             |
   bb.0:
     %0.subreg_hl32 = COPY %0.subreg_l32
     %1 = COPY %0.subreg_l64
     %2 = LARL @g_167
-    STC %1.subreg_l32, %2, 8, %noreg
+    STC %1.subreg_l32, %2, 8, $noreg
 
 ...
diff --git a/llvm/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll b/llvm/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll
index 0579d0d9800..a78cf992d8e 100644
--- a/llvm/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll
+++ b/llvm/test/CodeGen/SystemZ/store_nonbytesized_vecs.ll
@@ -80,7 +80,7 @@ define void @fun2(<8 x i32> %src, <8 x i31>* %p)
 ; CHECK-NEXT:    vlgvf %r1, %v24, 0
 ; CHECK-NEXT:    stc %r1, 30(%r2)
 ; CHECK-NEXT:    llgtr %r0, %r1
-; CHECK-NEXT:    # kill: def %r1l killed %r1l killed %r1d def %r1d
+; CHECK-NEXT:    # kill: def $r1l killed $r1l killed $r1d def $r1d
 ; CHECK-NEXT:    srl %r1, 8
 ; CHECK-NEXT:    sth %r1, 28(%r2)
 ; CHECK-NEXT:    vlgvf %r1, %v24, 1