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author | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2015-05-05 19:27:45 +0000 |
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committer | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2015-05-05 19:27:45 +0000 |
commit | 80b3af7ab3f8e76507cc4491be1460f1b1d8adb2 (patch) | |
tree | b9f2252bf5fb13308c25e7f05f918dfdae76aa77 /llvm/test/CodeGen/SystemZ/vec-move-01.ll | |
parent | cd808237b24c7d6d0bb7ddf577dba37c31a06a50 (diff) | |
download | bcm5719-llvm-80b3af7ab3f8e76507cc4491be1460f1b1d8adb2.tar.gz bcm5719-llvm-80b3af7ab3f8e76507cc4491be1460f1b1d8adb2.zip |
[SystemZ] Add CodeGen support for v4f32
The architecture doesn't really have any native v4f32 operations except
v4f32->v2f64 and v2f64->v4f32 conversions, with only half of the v4f32
elements being used. Even so, using vector registers for <4 x float>
and scalarising individual operations is much better than generating
completely scalar code, since there's much less register pressure.
It's also more efficient to do v4f32 comparisons by extending to 2
v2f64s, comparing those, then packing the result.
This particularly helps with llvmpipe.
Based on a patch by Richard Sandiford.
llvm-svn: 236523
Diffstat (limited to 'llvm/test/CodeGen/SystemZ/vec-move-01.ll')
-rw-r--r-- | llvm/test/CodeGen/SystemZ/vec-move-01.ll | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/SystemZ/vec-move-01.ll b/llvm/test/CodeGen/SystemZ/vec-move-01.ll index f9ae13b3ba1..896d24a1d20 100644 --- a/llvm/test/CodeGen/SystemZ/vec-move-01.ll +++ b/llvm/test/CodeGen/SystemZ/vec-move-01.ll @@ -34,6 +34,14 @@ define <2 x i64> @f4(<2 x i64> %val1, <2 x i64> %val2) { ret <2 x i64> %val2 } +; Test v4f32 moves. +define <4 x float> @f5(<4 x float> %val1, <4 x float> %val2) { +; CHECK-LABEL: f5: +; CHECK: vlr %v24, %v26 +; CHECK: br %r14 + ret <4 x float> %val2 +} + ; Test v2f64 moves. define <2 x double> @f6(<2 x double> %val1, <2 x double> %val2) { ; CHECK-LABEL: f6: |