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author | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2013-05-06 16:17:29 +0000 |
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committer | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2013-05-06 16:17:29 +0000 |
commit | 9e3577ff44fe5360c72fad02fbe931977f9235fb (patch) | |
tree | 23b3903f13f5307e8ee2d834a01ca56fc86b88ed /llvm/test/CodeGen/SystemZ/int-mul-01.ll | |
parent | 5f613dfd1f7edb0ae95d521b7107b582d9df5103 (diff) | |
download | bcm5719-llvm-9e3577ff44fe5360c72fad02fbe931977f9235fb.tar.gz bcm5719-llvm-9e3577ff44fe5360c72fad02fbe931977f9235fb.zip |
[SystemZ] Add CodeGen test cases
This adds all CodeGen tests for the SystemZ target.
This version of the patch incorporates feedback from a review by
Sean Silva. Thanks to all reviewers!
Patch by Richard Sandiford.
llvm-svn: 181204
Diffstat (limited to 'llvm/test/CodeGen/SystemZ/int-mul-01.ll')
-rw-r--r-- | llvm/test/CodeGen/SystemZ/int-mul-01.ll | 131 |
1 files changed, 131 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/SystemZ/int-mul-01.ll b/llvm/test/CodeGen/SystemZ/int-mul-01.ll new file mode 100644 index 00000000000..e1246e2156e --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/int-mul-01.ll @@ -0,0 +1,131 @@ +; Test 32-bit multiplication in which the second operand is a sign-extended +; i16 memory value. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s + +; Check the low end of the MH range. +define i32 @f1(i32 %lhs, i16 *%src) { +; CHECK: f1: +; CHECK: mh %r2, 0(%r3) +; CHECK: br %r14 + %half = load i16 *%src + %rhs = sext i16 %half to i32 + %res = mul i32 %lhs, %rhs + ret i32 %res +} + +; Check the high end of the aligned MH range. +define i32 @f2(i32 %lhs, i16 *%src) { +; CHECK: f2: +; CHECK: mh %r2, 4094(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 2047 + %half = load i16 *%ptr + %rhs = sext i16 %half to i32 + %res = mul i32 %lhs, %rhs + ret i32 %res +} + +; Check the next halfword up, which should use MHY instead of MH. +define i32 @f3(i32 %lhs, i16 *%src) { +; CHECK: f3: +; CHECK: mhy %r2, 4096(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 2048 + %half = load i16 *%ptr + %rhs = sext i16 %half to i32 + %res = mul i32 %lhs, %rhs + ret i32 %res +} + +; Check the high end of the aligned MHY range. +define i32 @f4(i32 %lhs, i16 *%src) { +; CHECK: f4: +; CHECK: mhy %r2, 524286(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 262143 + %half = load i16 *%ptr + %rhs = sext i16 %half to i32 + %res = mul i32 %lhs, %rhs + ret i32 %res +} + +; Check the next halfword up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i32 @f5(i32 %lhs, i16 *%src) { +; CHECK: f5: +; CHECK: agfi %r3, 524288 +; CHECK: mh %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 262144 + %half = load i16 *%ptr + %rhs = sext i16 %half to i32 + %res = mul i32 %lhs, %rhs + ret i32 %res +} + +; Check the high end of the negative aligned MHY range. +define i32 @f6(i32 %lhs, i16 *%src) { +; CHECK: f6: +; CHECK: mhy %r2, -2(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 -1 + %half = load i16 *%ptr + %rhs = sext i16 %half to i32 + %res = mul i32 %lhs, %rhs + ret i32 %res +} + +; Check the low end of the MHY range. +define i32 @f7(i32 %lhs, i16 *%src) { +; CHECK: f7: +; CHECK: mhy %r2, -524288(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 -262144 + %half = load i16 *%ptr + %rhs = sext i16 %half to i32 + %res = mul i32 %lhs, %rhs + ret i32 %res +} + +; Check the next halfword down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i32 @f8(i32 %lhs, i16 *%src) { +; CHECK: f8: +; CHECK: agfi %r3, -524290 +; CHECK: mh %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16 *%src, i64 -262145 + %half = load i16 *%ptr + %rhs = sext i16 %half to i32 + %res = mul i32 %lhs, %rhs + ret i32 %res +} + +; Check that MH allows an index. +define i32 @f9(i32 %lhs, i64 %src, i64 %index) { +; CHECK: f9: +; CHECK: mh %r2, 4094({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4094 + %ptr = inttoptr i64 %add2 to i16 * + %half = load i16 *%ptr + %rhs = sext i16 %half to i32 + %res = mul i32 %lhs, %rhs + ret i32 %res +} + +; Check that MHY allows an index. +define i32 @f10(i32 %lhs, i64 %src, i64 %index) { +; CHECK: f10: +; CHECK: mhy %r2, 4096({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 4096 + %ptr = inttoptr i64 %add2 to i16 * + %half = load i16 *%ptr + %rhs = sext i16 %half to i32 + %res = mul i32 %lhs, %rhs + ret i32 %res +} |