[SystemZ] Make the CCRegs regclass non-allocatable.

This was discovered to be necessary while running memchr-01.ll with
-verify-machinstrs, because it is not allowed to have a phys reg live
accross block boundaries while on SSA form, if the register is
allocatable (expect in entry block and landing pads).

In this test case, stringRRE pseudos are expanded after isel by adding
a loop block which produces a live out CC register. To make the test
pass, it was also necessary to not say that StringRRELoop pseudo uses
R0L, this is only true for the StringRRE opcode.

-verify-machineinstrs added to memchr-01.ll test.

New test case int-cmp-51.ll to test that MachineCSE can eliminate
an identical compare (which it couldn't do before).

Reviewed by Ulrich Weigand

llvm-svn: 251634

1 files changed, 34 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/SystemZ/int-cmp-51.ll b/llvm/test/CodeGen/SystemZ/int-cmp-51.ll
new file mode 100644
index 00000000000..85a0e4b4d3a
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/int-cmp-51.ll
@@ -0,0 +1,34 @@
+; Check that modelling of CC/CCRegs does not stop MachineCSE from
+; removing a compare.  MachineCSE will not extend a live range of an
+; allocatable or reserved phys reg.
+;
+; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
+
+declare void @bar(i8)
+
+; Check the low end of the CH range.
+define void @f1(i32 %lhs) {
+; CHECK-LABEL: BB#1:
+; CHECK-NOT: cijlh %r0, 1, .LBB0_3
+
+entry:
+  %and188 = and i32 %lhs, 255
+  %cmp189 = icmp ult i32 %and188, 2
+  br i1 %cmp189, label %if.then.191, label %if.else.201
+
+if.then.191:
+  %cmp194 = icmp eq i32 %and188, 1
+  br i1 %cmp194, label %if.then.196, label %if.else.198
+
+if.then.196:
+  call void @bar(i8 1);
+  br label %if.else.201
+
+if.else.198:
+  call void @bar(i8 0);
+  br label %if.else.201
+
+if.else.201:
+  ret void
+}
+