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| author | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2016-04-07 16:11:44 +0000 |
|---|---|---|
| committer | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2016-04-07 16:11:44 +0000 |
| commit | 2eb027d21f882e03f0658cddbdfee31efbf08663 (patch) | |
| tree | df88bad9a10f8b4870b77b2a2089a4a807962979 /llvm/test/CodeGen/SystemZ/int-cmp-41.ll | |
| parent | 14e351a553ea84d864174793a0a58b7ecda36c5d (diff) | |
| download | bcm5719-llvm-2eb027d21f882e03f0658cddbdfee31efbf08663.tar.gz bcm5719-llvm-2eb027d21f882e03f0658cddbdfee31efbf08663.zip | |
[SystemZ] Implement conditional returns
Return is now considered a predicable instruction, and is converted
to a newly-added CondReturn (which maps to BCR to %r14) instruction by
the if conversion pass.
Also, fused compare-and-branch transform knows about conditional
returns, emitting the proper fused instructions for them.
This transform triggers on a *lot* of tests, hence the huge diffstat.
The changes are mostly jX to br %r14 -> bXr %r14.
Author: koriakin
Differential Revision: http://reviews.llvm.org/D17339
llvm-svn: 265689
Diffstat (limited to 'llvm/test/CodeGen/SystemZ/int-cmp-41.ll')
| -rw-r--r-- | llvm/test/CodeGen/SystemZ/int-cmp-41.ll | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/llvm/test/CodeGen/SystemZ/int-cmp-41.ll b/llvm/test/CodeGen/SystemZ/int-cmp-41.ll index f4f5b4a0cf1..035de5733e9 100644 --- a/llvm/test/CodeGen/SystemZ/int-cmp-41.ll +++ b/llvm/test/CodeGen/SystemZ/int-cmp-41.ll @@ -10,7 +10,7 @@ define i64 @f1(i64 %src1) { ; CHECK-LABEL: f1: ; CHECK: cgfrl %r2, g -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 entry: %val = load i32 , i32 *@g @@ -47,7 +47,7 @@ exit: define i64 @f3(i64 %src1) { ; CHECK-LABEL: f3: ; CHECK: cgfrl %r2, g -; CHECK-NEXT: je +; CHECK-NEXT: ber %r14 ; CHECK: br %r14 entry: %val = load i32 , i32 *@g @@ -66,7 +66,7 @@ exit: define i64 @f4(i64 %src1) { ; CHECK-LABEL: f4: ; CHECK: cgfrl %r2, g -; CHECK-NEXT: jlh +; CHECK-NEXT: blhr %r14 ; CHECK: br %r14 entry: %val = load i32 , i32 *@g @@ -86,7 +86,7 @@ define i64 @f5(i64 %src1) { ; CHECK-LABEL: f5: ; CHECK: larl [[REG:%r[0-5]]], h ; CHECK: cgf %r2, 0([[REG]]) -; CHECK-NEXT: jl +; CHECK-NEXT: blr %r14 ; CHECK: br %r14 entry: %val = load i32 , i32 *@h, align 2 @@ -105,7 +105,7 @@ exit: define i64 @f6(i64 %src2) { ; CHECK-LABEL: f6: ; CHECK: cgfrl %r2, g -; CHECK-NEXT: jh {{\.L.*}} +; CHECK-NEXT: bhr %r14 ; CHECK: br %r14 entry: %val = load i32 , i32 *@g |
