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| author | David Blaikie <dblaikie@gmail.com> | 2015-02-27 21:17:42 +0000 |
|---|---|---|
| committer | David Blaikie <dblaikie@gmail.com> | 2015-02-27 21:17:42 +0000 |
| commit | a79ac14fa68297f9888bc70a10df5ed9b8864e38 (patch) | |
| tree | 8d8217a8928e3ee599bdde405e2e178b3a55b645 /llvm/test/CodeGen/SystemZ/frame-14.ll | |
| parent | 83687fb9e654c9d0086e7f6b728c26fa0b729e71 (diff) | |
| download | bcm5719-llvm-a79ac14fa68297f9888bc70a10df5ed9b8864e38.tar.gz bcm5719-llvm-a79ac14fa68297f9888bc70a10df5ed9b8864e38.zip | |
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
llvm-svn: 230794
Diffstat (limited to 'llvm/test/CodeGen/SystemZ/frame-14.ll')
| -rw-r--r-- | llvm/test/CodeGen/SystemZ/frame-14.ll | 38 |
1 files changed, 19 insertions, 19 deletions
diff --git a/llvm/test/CodeGen/SystemZ/frame-14.ll b/llvm/test/CodeGen/SystemZ/frame-14.ll index 21ef40a378f..3c080a40164 100644 --- a/llvm/test/CodeGen/SystemZ/frame-14.ll +++ b/llvm/test/CodeGen/SystemZ/frame-14.ll @@ -245,11 +245,11 @@ define void @f10(i32 *%vptr) { ; CHECK-FP: mvi 0([[REGISTER]]), 42 ; CHECK-FP: lg [[REGISTER]], [[OFFSET]](%r11) ; CHECK-FP: br %r14 - %i0 = load volatile i32 *%vptr - %i1 = load volatile i32 *%vptr - %i3 = load volatile i32 *%vptr - %i4 = load volatile i32 *%vptr - %i5 = load volatile i32 *%vptr + %i0 = load volatile i32 , i32 *%vptr + %i1 = load volatile i32 , i32 *%vptr + %i3 = load volatile i32 , i32 *%vptr + %i4 = load volatile i32 , i32 *%vptr + %i5 = load volatile i32 , i32 *%vptr %region1 = alloca [524104 x i8], align 8 %region2 = alloca [524104 x i8], align 8 %ptr1 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region1, i64 0, i64 8 @@ -278,20 +278,20 @@ define void @f11(i32 *%vptr) { ; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15) ; CHECK-NOFP: lmg %r6, %r15, ; CHECK-NOFP: br %r14 - %i0 = load volatile i32 *%vptr - %i1 = load volatile i32 *%vptr - %i3 = load volatile i32 *%vptr - %i4 = load volatile i32 *%vptr - %i5 = load volatile i32 *%vptr - %i6 = load volatile i32 *%vptr - %i7 = load volatile i32 *%vptr - %i8 = load volatile i32 *%vptr - %i9 = load volatile i32 *%vptr - %i10 = load volatile i32 *%vptr - %i11 = load volatile i32 *%vptr - %i12 = load volatile i32 *%vptr - %i13 = load volatile i32 *%vptr - %i14 = load volatile i32 *%vptr + %i0 = load volatile i32 , i32 *%vptr + %i1 = load volatile i32 , i32 *%vptr + %i3 = load volatile i32 , i32 *%vptr + %i4 = load volatile i32 , i32 *%vptr + %i5 = load volatile i32 , i32 *%vptr + %i6 = load volatile i32 , i32 *%vptr + %i7 = load volatile i32 , i32 *%vptr + %i8 = load volatile i32 , i32 *%vptr + %i9 = load volatile i32 , i32 *%vptr + %i10 = load volatile i32 , i32 *%vptr + %i11 = load volatile i32 , i32 *%vptr + %i12 = load volatile i32 , i32 *%vptr + %i13 = load volatile i32 , i32 *%vptr + %i14 = load volatile i32 , i32 *%vptr %region1 = alloca [524104 x i8], align 8 %region2 = alloca [524104 x i8], align 8 %ptr1 = getelementptr inbounds [524104 x i8], [524104 x i8]* %region1, i64 0, i64 8 |
