Add TargetLowering::prepareVolatileOrAtomicLoad

One unusual feature of the z architecture is that the result of a
previous load can be reused indefinitely for subsequent loads, even if
a cache-coherent store to that location is performed by another CPU.
A special serializing instruction must be used if you want to force
a load to be reattempted.

Since volatile loads are not supposed to be omitted in this way,
we should insert a serializing instruction before each such load.
The same goes for atomic loads.

The patch implements this at the IR->DAG boundary, in a similar way
to atomic fences.  It is a no-op for targets other than SystemZ.

llvm-svn: 196905

1 files changed, 1 insertions, 1 deletions

diff --git a/llvm/test/CodeGen/SystemZ/Large/branch-range-02.py b/llvm/test/CodeGen/SystemZ/Large/branch-range-02.py
index 0b21ced99a1..743e12de0f1 100644
--- a/llvm/test/CodeGen/SystemZ/Large/branch-range-02.py
+++ b/llvm/test/CodeGen/SystemZ/Large/branch-range-02.py
@@ -72,7 +72,7 @@ for i in xrange(blocks):
     print 'b%d:' % i
     print '  store volatile i8 %d, i8 *%%base' % value
     print '  %%astop%d = getelementptr i32 *%%stop, i64 %d' % (i, i)
-    print '  %%acur%d = load volatile i32 *%%astop%d' % (i, i)
+    print '  %%acur%d = load i32 *%%astop%d' % (i, i)
     print '  %%atest%d = icmp eq i32 %%limit, %%acur%d' % (i, i)
     print '  br i1 %%atest%d, label %%%s, label %%%s' % (i, other, next)