summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen/SPARC/multiple-div.ll
diff options
context:
space:
mode:
authorJames Y Knight <jyknight@google.com>2015-07-08 16:25:12 +0000
committerJames Y Knight <jyknight@google.com>2015-07-08 16:25:12 +0000
commitf238d176eb47a48b2775a3da4221afd5d5a05925 (patch)
tree64c70e2ec8c1de779f5967c5fc829a413b3f4e49 /llvm/test/CodeGen/SPARC/multiple-div.ll
parent51271bdc4ffc3986a0e9aa456bf254493f099f67 (diff)
downloadbcm5719-llvm-f238d176eb47a48b2775a3da4221afd5d5a05925.tar.gz
bcm5719-llvm-f238d176eb47a48b2775a3da4221afd5d5a05925.zip
[SPARC] Cleanup handling of the Y/ASR registers.
- Implement copying ASR to/from GPR regs. - Mark ASRs as non-allocatable, so it won't try to arbitrarily use them inappropriately. - Instead of inserting explicit WRASR/RDASR nodes in the MUL/DIV routines, just do normal register copies. - Also...mark div as using Y, not just writing it. Added a test case with some code which previously died with an assertion failure (with -O0), or produced wrong code (otherwise). (Third time's the charm?) Differential Revision: http://reviews.llvm.org/D10401 llvm-svn: 241686
Diffstat (limited to 'llvm/test/CodeGen/SPARC/multiple-div.ll')
-rw-r--r--llvm/test/CodeGen/SPARC/multiple-div.ll21
1 files changed, 21 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/SPARC/multiple-div.ll b/llvm/test/CodeGen/SPARC/multiple-div.ll
new file mode 100644
index 00000000000..6934f69ac18
--- /dev/null
+++ b/llvm/test/CodeGen/SPARC/multiple-div.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s -march=sparc | FileCheck %s
+; RUN: llc -O0 < %s -march=sparc | FileCheck %s
+
+;; llc -O0 used to try to spill Y to the stack, which isn't possible,
+;; and then crashed. Additionally, in -O1, it would omit the second
+;; apparently-redundant wr to %y, which is not actually redundant
+;; because the spec says to treat %y as potentially-written by udiv.
+
+; CHECK-LABEL: two_divides:
+; CHECK: wr %g0, %g0, %y
+; CHECK: udiv
+; CHECK: wr %g0, %g0, %y
+; CHECK: udiv
+; CHECK: add
+
+define i32 @two_divides(i32 %a, i32 %b) {
+ %r = udiv i32 %a, %b
+ %r2 = udiv i32 %b, %a
+ %r3 = add i32 %r, %r2
+ ret i32 %r3
+}
OpenPOWER on IntegriCloud