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| author | Alex Bradbury <asb@lowrisc.org> | 2017-12-11 12:34:11 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2017-12-11 12:34:11 +0000 |
| commit | b014e3de52fd50dc2c185f0c54a3f3783292ee78 (patch) | |
| tree | b5048a14b21825db8561a88fa71e5cf4456008fe /llvm/test/CodeGen/RISCV/imm.ll | |
| parent | 220b1c13bf2b80a3273f0062096f23a8978a795a (diff) | |
| download | bcm5719-llvm-b014e3de52fd50dc2c185f0c54a3f3783292ee78.tar.gz bcm5719-llvm-b014e3de52fd50dc2c185f0c54a3f3783292ee78.zip | |
[RISCV] Implement prolog and epilog insertion
As frame pointer elimination isn't implemented until a later patch and we make
extensive use of update_llc_test_checks.py, this changes touches a lot of the
RISC-V tests.
Differential Revision: https://reviews.llvm.org/D39849
llvm-svn: 320357
Diffstat (limited to 'llvm/test/CodeGen/RISCV/imm.ll')
| -rw-r--r-- | llvm/test/CodeGen/RISCV/imm.ll | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/RISCV/imm.ll b/llvm/test/CodeGen/RISCV/imm.ll index ddefa22835a..e33dd2b8d1e 100644 --- a/llvm/test/CodeGen/RISCV/imm.ll +++ b/llvm/test/CodeGen/RISCV/imm.ll @@ -7,7 +7,14 @@ define i32 @zero() nounwind { ; RV32I-LABEL: zero: ; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: sw ra, 12(sp) +; RV32I-NEXT: sw s0, 8(sp) +; RV32I-NEXT: addi s0, sp, 16 ; RV32I-NEXT: addi a0, zero, 0 +; RV32I-NEXT: lw s0, 8(sp) +; RV32I-NEXT: lw ra, 12(sp) +; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: jalr zero, ra, 0 ret i32 0 } @@ -15,7 +22,14 @@ define i32 @zero() nounwind { define i32 @pos_small() nounwind { ; RV32I-LABEL: pos_small: ; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: sw ra, 12(sp) +; RV32I-NEXT: sw s0, 8(sp) +; RV32I-NEXT: addi s0, sp, 16 ; RV32I-NEXT: addi a0, zero, 2047 +; RV32I-NEXT: lw s0, 8(sp) +; RV32I-NEXT: lw ra, 12(sp) +; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: jalr zero, ra, 0 ret i32 2047 } @@ -23,7 +37,14 @@ define i32 @pos_small() nounwind { define i32 @neg_small() nounwind { ; RV32I-LABEL: neg_small: ; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: sw ra, 12(sp) +; RV32I-NEXT: sw s0, 8(sp) +; RV32I-NEXT: addi s0, sp, 16 ; RV32I-NEXT: addi a0, zero, -2048 +; RV32I-NEXT: lw s0, 8(sp) +; RV32I-NEXT: lw ra, 12(sp) +; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: jalr zero, ra, 0 ret i32 -2048 } @@ -31,8 +52,15 @@ define i32 @neg_small() nounwind { define i32 @pos_i32() nounwind { ; RV32I-LABEL: pos_i32: ; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: sw ra, 12(sp) +; RV32I-NEXT: sw s0, 8(sp) +; RV32I-NEXT: addi s0, sp, 16 ; RV32I-NEXT: lui a0, 423811 ; RV32I-NEXT: addi a0, a0, -1297 +; RV32I-NEXT: lw s0, 8(sp) +; RV32I-NEXT: lw ra, 12(sp) +; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: jalr zero, ra, 0 ret i32 1735928559 } @@ -40,8 +68,15 @@ define i32 @pos_i32() nounwind { define i32 @neg_i32() nounwind { ; RV32I-LABEL: neg_i32: ; RV32I: # %bb.0: +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: sw ra, 12(sp) +; RV32I-NEXT: sw s0, 8(sp) +; RV32I-NEXT: addi s0, sp, 16 ; RV32I-NEXT: lui a0, 912092 ; RV32I-NEXT: addi a0, a0, -273 +; RV32I-NEXT: lw s0, 8(sp) +; RV32I-NEXT: lw ra, 12(sp) +; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: jalr zero, ra, 0 ret i32 -559038737 } |
