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authorAlex Bradbury <asb@lowrisc.org>2018-04-18 20:34:23 +0000
committerAlex Bradbury <asb@lowrisc.org>2018-04-18 20:34:23 +0000
commit3ff2022bb940237f10584d81da8d21bd62e76c7d (patch)
tree41284359b11859abf59ef75e2a3b238a7da3362b /llvm/test/CodeGen/RISCV/imm.ll
parentf4a3ff008d58fca4031f03644d96a634cd9815ba (diff)
downloadbcm5719-llvm-3ff2022bb940237f10584d81da8d21bd62e76c7d.tar.gz
bcm5719-llvm-3ff2022bb940237f10584d81da8d21bd62e76c7d.zip
[RISCV] Introduce pattern for materialising immediates with 0 for lower 12 bits
These immediates can be materialised with just an lui, rather than an lui+addi pair. llvm-svn: 330293
Diffstat (limited to 'llvm/test/CodeGen/RISCV/imm.ll')
-rw-r--r--llvm/test/CodeGen/RISCV/imm.ll2
1 files changed, 0 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/RISCV/imm.ll b/llvm/test/CodeGen/RISCV/imm.ll
index ae104243acc..b9e2f8a40c6 100644
--- a/llvm/test/CodeGen/RISCV/imm.ll
+++ b/llvm/test/CodeGen/RISCV/imm.ll
@@ -50,7 +50,6 @@ define i32 @pos_i32_hi20_only() nounwind {
; RV32I-LABEL: pos_i32_hi20_only:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a0, 16
-; RV32I-NEXT: mv a0, a0
; RV32I-NEXT: ret
ret i32 65536
}
@@ -59,7 +58,6 @@ define i32 @neg_i32_hi20_only() nounwind {
; RV32I-LABEL: neg_i32_hi20_only:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a0, 1048560
-; RV32I-NEXT: mv a0, a0
; RV32I-NEXT: ret
ret i32 -65536
}
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