[RISCV] Support and tests for a variety of additional LLVM IR constructs

Previous patches primarily ensured that codegen was possible for the standard
RISC-V instructions. However, there are a number of IR inputs that wouldn't be
appropriately lowered. This patch both adds test cases and supports lowering
for a number of these cases:
* Improved sext/zext/trunc support
* Support for setcc variants that don't map directly to RISC-V instructions
* Lowering mul, and hence support for external symbols
* addc, adde, subc, sube
* mulhs, srem, mulhu, urem, udiv, sdiv
* {srl,sra,shl}_parts
* brind
* br_jt
* bswap, ctlz, cttz, ctpop
* rotl, rotr
* BlockAddress operands

Differential Revision: https://reviews.llvm.org/D29938

llvm-svn: 318737

1 files changed, 114 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/RISCV/i32-icmp.ll b/llvm/test/CodeGen/RISCV/i32-icmp.ll
new file mode 100644
index 00000000000..4d86ced2584
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/i32-icmp.ll
@@ -0,0 +1,114 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=RV32I
+
+; TODO: check the generated instructions for the equivalent of seqz, snez,
+; sltz, sgtz map to something simple
+
+define i32 @icmp_eq(i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: icmp_eq:
+; RV32I:       # BB#0:
+; RV32I-NEXT:    xor a0, a0, a1
+; RV32I-NEXT:    sltiu a0, a0, 1
+; RV32I-NEXT:    jalr zero, ra, 0
+  %1 = icmp eq i32 %a, %b
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
+define i32 @icmp_ne(i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: icmp_ne:
+; RV32I:       # BB#0:
+; RV32I-NEXT:    xor a0, a0, a1
+; RV32I-NEXT:    sltu a0, zero, a0
+; RV32I-NEXT:    jalr zero, ra, 0
+  %1 = icmp ne i32 %a, %b
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
+define i32 @icmp_ugt(i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: icmp_ugt:
+; RV32I:       # BB#0:
+; RV32I-NEXT:    sltu a0, a1, a0
+; RV32I-NEXT:    jalr zero, ra, 0
+  %1 = icmp ugt i32 %a, %b
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
+define i32 @icmp_uge(i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: icmp_uge:
+; RV32I:       # BB#0:
+; RV32I-NEXT:    sltu a0, a0, a1
+; RV32I-NEXT:    xori a0, a0, 1
+; RV32I-NEXT:    jalr zero, ra, 0
+  %1 = icmp uge i32 %a, %b
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
+define i32 @icmp_ult(i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: icmp_ult:
+; RV32I:       # BB#0:
+; RV32I-NEXT:    sltu a0, a0, a1
+; RV32I-NEXT:    jalr zero, ra, 0
+  %1 = icmp ult i32 %a, %b
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
+define i32 @icmp_ule(i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: icmp_ule:
+; RV32I:       # BB#0:
+; RV32I-NEXT:    sltu a0, a1, a0
+; RV32I-NEXT:    xori a0, a0, 1
+; RV32I-NEXT:    jalr zero, ra, 0
+  %1 = icmp ule i32 %a, %b
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
+define i32 @icmp_sgt(i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: icmp_sgt:
+; RV32I:       # BB#0:
+; RV32I-NEXT:    slt a0, a1, a0
+; RV32I-NEXT:    jalr zero, ra, 0
+  %1 = icmp sgt i32 %a, %b
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
+define i32 @icmp_sge(i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: icmp_sge:
+; RV32I:       # BB#0:
+; RV32I-NEXT:    slt a0, a0, a1
+; RV32I-NEXT:    xori a0, a0, 1
+; RV32I-NEXT:    jalr zero, ra, 0
+  %1 = icmp sge i32 %a, %b
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
+define i32 @icmp_slt(i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: icmp_slt:
+; RV32I:       # BB#0:
+; RV32I-NEXT:    slt a0, a0, a1
+; RV32I-NEXT:    jalr zero, ra, 0
+  %1 = icmp slt i32 %a, %b
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
+define i32 @icmp_sle(i32 %a, i32 %b) nounwind {
+; RV32I-LABEL: icmp_sle:
+; RV32I:       # BB#0:
+; RV32I-NEXT:    slt a0, a1, a0
+; RV32I-NEXT:    xori a0, a0, 1
+; RV32I-NEXT:    jalr zero, ra, 0
+  %1 = icmp sle i32 %a, %b
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
+; TODO: check variants with an immediate?