[RISCV] Add RV64F codegen support

This requires a little extra work due tothe fact i32 is not a legal type. When
call lowering happens post-legalisation (e.g. when an intrinsic was inserted
during legalisation). A bitcast from f32 to i32 can't be introduced. This is
similar to the challenges with RV32D. To handle this, we introduce
target-specific DAG nodes that perform bitcast+anyext for f32->i64 and
trunc+bitcast for i64->f32.

Differential Revision: https://reviews.llvm.org/D53235

llvm-svn: 352807

1 files changed, 134 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/RISCV/float-fcmp.ll b/llvm/test/CodeGen/RISCV/float-fcmp.ll
index c8942a90eb7..16f44184791 100644
--- a/llvm/test/CodeGen/RISCV/float-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/float-fcmp.ll
@@ -1,12 +1,19 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32IF %s
+; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV64IF %s
 
 define i32 @fcmp_false(float %a, float %b) nounwind {
 ; RV32IF-LABEL: fcmp_false:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    mv a0, zero
 ; RV32IF-NEXT:    ret
+;
+; RV64IF-LABEL: fcmp_false:
+; RV64IF:       # %bb.0:
+; RV64IF-NEXT:    mv a0, zero
+; RV64IF-NEXT:    ret
   %1 = fcmp false float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
@@ -19,6 +26,13 @@ define i32 @fcmp_oeq(float %a, float %b) nounwind {
 ; RV32IF-NEXT:    fmv.w.x ft1, a0
 ; RV32IF-NEXT:    feq.s a0, ft1, ft0
 ; RV32IF-NEXT:    ret
+;
+; RV64IF-LABEL: fcmp_oeq:
+; RV64IF:       # %bb.0:
+; RV64IF-NEXT:    fmv.w.x ft0, a1
+; RV64IF-NEXT:    fmv.w.x ft1, a0
+; RV64IF-NEXT:    feq.s a0, ft1, ft0
+; RV64IF-NEXT:    ret
   %1 = fcmp oeq float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
@@ -31,6 +45,13 @@ define i32 @fcmp_ogt(float %a, float %b) nounwind {
 ; RV32IF-NEXT:    fmv.w.x ft1, a1
 ; RV32IF-NEXT:    flt.s a0, ft1, ft0
 ; RV32IF-NEXT:    ret
+;
+; RV64IF-LABEL: fcmp_ogt:
+; RV64IF:       # %bb.0:
+; RV64IF-NEXT:    fmv.w.x ft0, a0
+; RV64IF-NEXT:    fmv.w.x ft1, a1
+; RV64IF-NEXT:    flt.s a0, ft1, ft0
+; RV64IF-NEXT:    ret
   %1 = fcmp ogt float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
@@ -43,6 +64,13 @@ define i32 @fcmp_oge(float %a, float %b) nounwind {
 ; RV32IF-NEXT:    fmv.w.x ft1, a1
 ; RV32IF-NEXT:    fle.s a0, ft1, ft0
 ; RV32IF-NEXT:    ret
+;
+; RV64IF-LABEL: fcmp_oge:
+; RV64IF:       # %bb.0:
+; RV64IF-NEXT:    fmv.w.x ft0, a0
+; RV64IF-NEXT:    fmv.w.x ft1, a1
+; RV64IF-NEXT:    fle.s a0, ft1, ft0
+; RV64IF-NEXT:    ret
   %1 = fcmp oge float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
@@ -55,6 +83,13 @@ define i32 @fcmp_olt(float %a, float %b) nounwind {
 ; RV32IF-NEXT:    fmv.w.x ft1, a0
 ; RV32IF-NEXT:    flt.s a0, ft1, ft0
 ; RV32IF-NEXT:    ret
+;
+; RV64IF-LABEL: fcmp_olt:
+; RV64IF:       # %bb.0:
+; RV64IF-NEXT:    fmv.w.x ft0, a1
+; RV64IF-NEXT:    fmv.w.x ft1, a0
+; RV64IF-NEXT:    flt.s a0, ft1, ft0
+; RV64IF-NEXT:    ret
   %1 = fcmp olt float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
@@ -67,6 +102,13 @@ define i32 @fcmp_ole(float %a, float %b) nounwind {
 ; RV32IF-NEXT:    fmv.w.x ft1, a0
 ; RV32IF-NEXT:    fle.s a0, ft1, ft0
 ; RV32IF-NEXT:    ret
+;
+; RV64IF-LABEL: fcmp_ole:
+; RV64IF:       # %bb.0:
+; RV64IF-NEXT:    fmv.w.x ft0, a1
+; RV64IF-NEXT:    fmv.w.x ft1, a0
+; RV64IF-NEXT:    fle.s a0, ft1, ft0
+; RV64IF-NEXT:    ret
   %1 = fcmp ole float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
@@ -86,6 +128,20 @@ define i32 @fcmp_one(float %a, float %b) nounwind {
 ; RV32IF-NEXT:    xori a0, a0, 1
 ; RV32IF-NEXT:    and a0, a1, a0
 ; RV32IF-NEXT:    ret
+;
+; RV64IF-LABEL: fcmp_one:
+; RV64IF:       # %bb.0:
+; RV64IF-NEXT:    fmv.w.x ft0, a0
+; RV64IF-NEXT:    fmv.w.x ft1, a1
+; RV64IF-NEXT:    feq.s a0, ft1, ft1
+; RV64IF-NEXT:    feq.s a1, ft0, ft0
+; RV64IF-NEXT:    and a0, a1, a0
+; RV64IF-NEXT:    feq.s a1, ft0, ft1
+; RV64IF-NEXT:    not a1, a1
+; RV64IF-NEXT:    seqz a0, a0
+; RV64IF-NEXT:    xori a0, a0, 1
+; RV64IF-NEXT:    and a0, a1, a0
+; RV64IF-NEXT:    ret
   %1 = fcmp one float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
@@ -102,6 +158,17 @@ define i32 @fcmp_ord(float %a, float %b) nounwind {
 ; RV32IF-NEXT:    seqz a0, a0
 ; RV32IF-NEXT:    xori a0, a0, 1
 ; RV32IF-NEXT:    ret
+;
+; RV64IF-LABEL: fcmp_ord:
+; RV64IF:       # %bb.0:
+; RV64IF-NEXT:    fmv.w.x ft0, a1
+; RV64IF-NEXT:    feq.s a1, ft0, ft0
+; RV64IF-NEXT:    fmv.w.x ft0, a0
+; RV64IF-NEXT:    feq.s a0, ft0, ft0
+; RV64IF-NEXT:    and a0, a0, a1
+; RV64IF-NEXT:    seqz a0, a0
+; RV64IF-NEXT:    xori a0, a0, 1
+; RV64IF-NEXT:    ret
   %1 = fcmp ord float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
@@ -119,6 +186,18 @@ define i32 @fcmp_ueq(float %a, float %b) nounwind {
 ; RV32IF-NEXT:    seqz a1, a1
 ; RV32IF-NEXT:    or a0, a0, a1
 ; RV32IF-NEXT:    ret
+;
+; RV64IF-LABEL: fcmp_ueq:
+; RV64IF:       # %bb.0:
+; RV64IF-NEXT:    fmv.w.x ft0, a1
+; RV64IF-NEXT:    fmv.w.x ft1, a0
+; RV64IF-NEXT:    feq.s a0, ft1, ft0
+; RV64IF-NEXT:    feq.s a1, ft0, ft0
+; RV64IF-NEXT:    feq.s a2, ft1, ft1
+; RV64IF-NEXT:    and a1, a2, a1
+; RV64IF-NEXT:    seqz a1, a1
+; RV64IF-NEXT:    or a0, a0, a1
+; RV64IF-NEXT:    ret
   %1 = fcmp ueq float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
@@ -132,6 +211,14 @@ define i32 @fcmp_ugt(float %a, float %b) nounwind {
 ; RV32IF-NEXT:    fle.s a0, ft1, ft0
 ; RV32IF-NEXT:    xori a0, a0, 1
 ; RV32IF-NEXT:    ret
+;
+; RV64IF-LABEL: fcmp_ugt:
+; RV64IF:       # %bb.0:
+; RV64IF-NEXT:    fmv.w.x ft0, a1
+; RV64IF-NEXT:    fmv.w.x ft1, a0
+; RV64IF-NEXT:    fle.s a0, ft1, ft0
+; RV64IF-NEXT:    xori a0, a0, 1
+; RV64IF-NEXT:    ret
   %1 = fcmp ugt float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
@@ -145,6 +232,14 @@ define i32 @fcmp_uge(float %a, float %b) nounwind {
 ; RV32IF-NEXT:    flt.s a0, ft1, ft0
 ; RV32IF-NEXT:    xori a0, a0, 1
 ; RV32IF-NEXT:    ret
+;
+; RV64IF-LABEL: fcmp_uge:
+; RV64IF:       # %bb.0:
+; RV64IF-NEXT:    fmv.w.x ft0, a1
+; RV64IF-NEXT:    fmv.w.x ft1, a0
+; RV64IF-NEXT:    flt.s a0, ft1, ft0
+; RV64IF-NEXT:    xori a0, a0, 1
+; RV64IF-NEXT:    ret
   %1 = fcmp uge float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
@@ -158,6 +253,14 @@ define i32 @fcmp_ult(float %a, float %b) nounwind {
 ; RV32IF-NEXT:    fle.s a0, ft1, ft0
 ; RV32IF-NEXT:    xori a0, a0, 1
 ; RV32IF-NEXT:    ret
+;
+; RV64IF-LABEL: fcmp_ult:
+; RV64IF:       # %bb.0:
+; RV64IF-NEXT:    fmv.w.x ft0, a0
+; RV64IF-NEXT:    fmv.w.x ft1, a1
+; RV64IF-NEXT:    fle.s a0, ft1, ft0
+; RV64IF-NEXT:    xori a0, a0, 1
+; RV64IF-NEXT:    ret
   %1 = fcmp ult float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
@@ -171,6 +274,14 @@ define i32 @fcmp_ule(float %a, float %b) nounwind {
 ; RV32IF-NEXT:    flt.s a0, ft1, ft0
 ; RV32IF-NEXT:    xori a0, a0, 1
 ; RV32IF-NEXT:    ret
+;
+; RV64IF-LABEL: fcmp_ule:
+; RV64IF:       # %bb.0:
+; RV64IF-NEXT:    fmv.w.x ft0, a0
+; RV64IF-NEXT:    fmv.w.x ft1, a1
+; RV64IF-NEXT:    flt.s a0, ft1, ft0
+; RV64IF-NEXT:    xori a0, a0, 1
+; RV64IF-NEXT:    ret
   %1 = fcmp ule float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
@@ -184,6 +295,14 @@ define i32 @fcmp_une(float %a, float %b) nounwind {
 ; RV32IF-NEXT:    feq.s a0, ft1, ft0
 ; RV32IF-NEXT:    xori a0, a0, 1
 ; RV32IF-NEXT:    ret
+;
+; RV64IF-LABEL: fcmp_une:
+; RV64IF:       # %bb.0:
+; RV64IF-NEXT:    fmv.w.x ft0, a1
+; RV64IF-NEXT:    fmv.w.x ft1, a0
+; RV64IF-NEXT:    feq.s a0, ft1, ft0
+; RV64IF-NEXT:    xori a0, a0, 1
+; RV64IF-NEXT:    ret
   %1 = fcmp une float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
@@ -199,6 +318,16 @@ define i32 @fcmp_uno(float %a, float %b) nounwind {
 ; RV32IF-NEXT:    and a0, a0, a1
 ; RV32IF-NEXT:    seqz a0, a0
 ; RV32IF-NEXT:    ret
+;
+; RV64IF-LABEL: fcmp_uno:
+; RV64IF:       # %bb.0:
+; RV64IF-NEXT:    fmv.w.x ft0, a1
+; RV64IF-NEXT:    feq.s a1, ft0, ft0
+; RV64IF-NEXT:    fmv.w.x ft0, a0
+; RV64IF-NEXT:    feq.s a0, ft0, ft0
+; RV64IF-NEXT:    and a0, a0, a1
+; RV64IF-NEXT:    seqz a0, a0
+; RV64IF-NEXT:    ret
   %1 = fcmp uno float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
@@ -209,6 +338,11 @@ define i32 @fcmp_true(float %a, float %b) nounwind {
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi a0, zero, 1
 ; RV32IF-NEXT:    ret
+;
+; RV64IF-LABEL: fcmp_true:
+; RV64IF:       # %bb.0:
+; RV64IF-NEXT:    addi a0, zero, 1
+; RV64IF-NEXT:    ret
   %1 = fcmp true float %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2