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| author | Alex Bradbury <asb@lowrisc.org> | 2019-03-30 09:15:47 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2019-03-30 09:15:47 +0000 |
| commit | 9681b01c214fc6a8d130e2421bfb1ca1568452e5 (patch) | |
| tree | 2f8d24422b2d22a5212eecd0e34a1f4c8b8ddc0d /llvm/test/CodeGen/RISCV/double-previous-failure.ll | |
| parent | d880de2d19d46f7cfea7aa593602458440bc1e8d (diff) | |
| download | bcm5719-llvm-9681b01c214fc6a8d130e2421bfb1ca1568452e5.tar.gz bcm5719-llvm-9681b01c214fc6a8d130e2421bfb1ca1568452e5.zip | |
[RISCV] Add DAGCombine for (SplitF64 (ConstantFP x))
The SplitF64 node is used on RV32D to convert an f64 directly to a pair of i32
(necessary as bitcasting to i64 isn't legal). When performed on a ConstantFP,
this will result in a FP load from the constant pool followed by a store to
the stack and two integer loads from the stack (necessary as there is no way
to directly move between f64 FPRs and i32 GPRs on RV32D). It's always cheaper
to just materialise integers for the lo and hi parts of the FP constant, so do
that instead.
llvm-svn: 357341
Diffstat (limited to 'llvm/test/CodeGen/RISCV/double-previous-failure.ll')
| -rw-r--r-- | llvm/test/CodeGen/RISCV/double-previous-failure.ll | 18 |
1 files changed, 7 insertions, 11 deletions
diff --git a/llvm/test/CodeGen/RISCV/double-previous-failure.ll b/llvm/test/CodeGen/RISCV/double-previous-failure.ll index 3a07e5d5858..168c6c2e67d 100644 --- a/llvm/test/CodeGen/RISCV/double-previous-failure.ll +++ b/llvm/test/CodeGen/RISCV/double-previous-failure.ll @@ -17,24 +17,20 @@ define i32 @main() nounwind { ; RV32IFD: # %bb.0: # %entry ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) -; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0) -; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI1_0) -; RV32IFD-NEXT: fld ft0, 0(a0) -; RV32IFD-NEXT: fsd ft0, 0(sp) -; RV32IFD-NEXT: lw a0, 0(sp) -; RV32IFD-NEXT: lw a1, 4(sp) +; RV32IFD-NEXT: mv a0, zero +; RV32IFD-NEXT: lui a1, 262144 ; RV32IFD-NEXT: call test -; RV32IFD-NEXT: lui a2, %hi(.LCPI1_1) -; RV32IFD-NEXT: addi a2, a2, %lo(.LCPI1_1) -; RV32IFD-NEXT: fld ft1, 0(a2) ; RV32IFD-NEXT: sw a0, 0(sp) ; RV32IFD-NEXT: sw a1, 4(sp) ; RV32IFD-NEXT: fld ft0, 0(sp) +; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0) +; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI1_0) +; RV32IFD-NEXT: fld ft1, 0(a0) ; RV32IFD-NEXT: flt.d a0, ft0, ft1 ; RV32IFD-NEXT: bnez a0, .LBB1_3 ; RV32IFD-NEXT: # %bb.1: # %entry -; RV32IFD-NEXT: lui a0, %hi(.LCPI1_2) -; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI1_2) +; RV32IFD-NEXT: lui a0, %hi(.LCPI1_1) +; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI1_1) ; RV32IFD-NEXT: fld ft1, 0(a0) ; RV32IFD-NEXT: flt.d a0, ft1, ft0 ; RV32IFD-NEXT: xori a0, a0, 1 |
