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| author | Alex Bradbury <asb@lowrisc.org> | 2019-01-11 19:46:48 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2019-01-11 19:46:48 +0000 |
| commit | eea0b07028c41f7979d4ddde12efd97db3139c62 (patch) | |
| tree | aa3ea7f154c635df9b49a95a1b31b9ef1b5d2ffe /llvm/test/CodeGen/RISCV/atomic-fence.ll | |
| parent | 946fe976fded7fb2784e3662e905d63743cf4aec (diff) | |
| download | bcm5719-llvm-eea0b07028c41f7979d4ddde12efd97db3139c62.tar.gz bcm5719-llvm-eea0b07028c41f7979d4ddde12efd97db3139c62.zip | |
[RISCV][NFC] Add CHECK lines for atomic operations on RV64I
As or RV32I, we include these for completeness. Committing now to make it
easier to review the RV64A patch.
llvm-svn: 350962
Diffstat (limited to 'llvm/test/CodeGen/RISCV/atomic-fence.ll')
| -rw-r--r-- | llvm/test/CodeGen/RISCV/atomic-fence.ll | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/RISCV/atomic-fence.ll b/llvm/test/CodeGen/RISCV/atomic-fence.ll index 174977d98d6..120f65bfcfd 100644 --- a/llvm/test/CodeGen/RISCV/atomic-fence.ll +++ b/llvm/test/CodeGen/RISCV/atomic-fence.ll @@ -3,12 +3,21 @@ ; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s +; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefix=RV64I %s +; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \ +; RUN: | FileCheck -check-prefix=RV64I %s define void @fence_acquire() nounwind { ; RV32I-LABEL: fence_acquire: ; RV32I: # %bb.0: ; RV32I-NEXT: fence r, rw ; RV32I-NEXT: ret +; +; RV64I-LABEL: fence_acquire: +; RV64I: # %bb.0: +; RV64I-NEXT: fence r, rw +; RV64I-NEXT: ret fence acquire ret void } @@ -18,6 +27,11 @@ define void @fence_release() nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: fence rw, w ; RV32I-NEXT: ret +; +; RV64I-LABEL: fence_release: +; RV64I: # %bb.0: +; RV64I-NEXT: fence rw, w +; RV64I-NEXT: ret fence release ret void } @@ -27,6 +41,11 @@ define void @fence_acq_rel() nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: fence.tso ; RV32I-NEXT: ret +; +; RV64I-LABEL: fence_acq_rel: +; RV64I: # %bb.0: +; RV64I-NEXT: fence.tso +; RV64I-NEXT: ret fence acq_rel ret void } @@ -36,6 +55,11 @@ define void @fence_seq_cst() nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: fence rw, rw ; RV32I-NEXT: ret +; +; RV64I-LABEL: fence_seq_cst: +; RV64I: # %bb.0: +; RV64I-NEXT: fence rw, rw +; RV64I-NEXT: ret fence seq_cst ret void } |
